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公开(公告)号：US20230137079A1
公开(公告)日：2023-05-04
申请号：US17514847
申请日：2021-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： GIACOMO PEDRETTI , JOHN PAUL STRACHAN , CATHERINE GRAVES
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
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公开(公告)号：US20210035640A1
公开(公告)日：2021-02-04
申请号：US16526455
申请日：2019-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： CAN LI , CATHERINE GRAVES , JOHN PAUL STRACHAN
IPC: G11C15/04
Abstract: A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
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公开(公告)号：US20200242448A1
公开(公告)日：2020-07-30
申请号：US16261398
申请日：2019-01-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： JOHN PAUL STRACHAN , SUHAS KUMAR , THOMAS VAN VAERENBERGH
Abstract: Staged neural networks and methods therefor are provided for solving NP hard/complete problems. In some embodiments, the methods include identifying a plurality of second NP hard/complete problems, wherein each of the second NP hard/complete problems is similar to the first NP hard/complete problem; identifying solutions to the second NP hard/complete problems; training a deep neural network with the second NP hard/complete problems and the solutions; providing the first NP hard/complete problem to the trained deep neural network, wherein the trained deep neural network generates a preliminary solution to the first NP hard/complete problem; and providing the preliminary solution to a recursive neural network configured to execute an energy minimization search, wherein the recursive neural network generates a final solution to the problem based on the preliminary solution.
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公开(公告)号：US20230019942A1
公开(公告)日：2023-01-19
申请号：US17378650
申请日：2021-07-16
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： SUHAS KUMAR , JOHN PAUL STRACHAN , THOMAS VAN VAERENBERGH
Abstract: Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is “gradually” provided to the network of memristors. A solution to the second problem can be determined.
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公开(公告)号：US20210125667A1
公开(公告)日：2021-04-29
申请号：US16667773
申请日：2019-10-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： AMIT SHARMA , JOHN PAUL STRACHAN , SUHAS KUMAR , CATHERINE GRAVES , MARTIN FOLTIN , CRAIG WARNER
IPC: G11C13/00
Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.
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Patent Agency Ranking
公开(公告)号：US20230246655A1
公开(公告)日：2023-08-03
申请号：US17580146
申请日：2022-01-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： JOHN PAUL STRACHAN , CAN LI , CATHERINE GRAVES
CPC classification number: H03M13/1575 , G11C13/004 , G11C13/0069 , G11C27/005 , H03M13/1177 , H03M13/6597
Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other nonvolatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.
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公开(公告)号：US20230197151A1
公开(公告)日：2023-06-22
申请号：US17555260
申请日：2021-12-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： CATHERINE GRAVES , GIACOMO PEDRETTI , SERGEY SEREBRYAKOV , JOHN PAUL STRACHAN
CPC classification number: G11C13/004 , G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C15/04 , G06N7/005
Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.
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公开(公告)号：US20220351794A1
公开(公告)日：2022-11-03
申请号：US17245540
申请日：2021-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： CATHERINE GRAVES , CAN LI , JOHN PAUL STRACHAN
Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.
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公开(公告)号：US20220138204A1
公开(公告)日：2022-05-05
申请号：US17085805
申请日：2020-10-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： CATHERINE GRAVES , CAN LI , JOHN PAUL STRACHAN , DEJAN S. MILOJICIC , KIMBERLY KEETON
IPC: G06F16/2455 , G06F16/22 , G06F16/901 , G06F1/3296 , G06F1/3206 , G11C27/00 , G11C13/00
Abstract: Encoding of domain logic rules in an analog content addressable memory (aCAM) is disclosed. By encoding domain logic in an aCAM, rapid and flexible search capabilities are enabled, including the capability to search ranges of analog values, fuzzy match capabilities, and optimized parameter search capabilities. This is achieved with low latency by using only a small number of clock cycles at low power. A domain logic ruleset may be represented using various data structures such as decision trees, directed graphs, or the like. These representations can be converted to a table of values, where each table column can be directly mapped to a corresponding row of the aCAM.
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公开(公告)号：US20190189180A1
公开(公告)日：2019-06-20
申请号：US16283513
申请日：2019-02-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： NING GE , JOHN PAUL STRACHAN , JIANHUA YANG , MIAO HU
Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
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