公开(公告)号：US11934840B2

公开(公告)日：2024-03-19

申请号：US17231554

申请日：2021-04-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Somasundaram Arunachalam ,  Debdipta Ghosh

IPC: G06F15/177 ,  G06F9/4401 ,  G06F9/50 ,  G06F18/214 ,  G06N7/01

CPC classification number: G06F9/4403 ,  G06F9/4411 ,  G06F9/5044 ,  G06F18/214 ,  G06N7/01 ,  G06F9/4406

Abstract: Approaches for classifying hardware components of a computing device using a classification system are described. In an example, by the classification system, a hardware configuration information of the computing device installed within a networked environment is obtained. The hardware configuration information may thus be processed based on a system classification model. The system classification model is to classify hardware components of the computing device as one of a plurality of hardware types. Once the hardware components are classified, a category of the computing device is determined. Based on the determined category, a target system software is identified and installed onto the computing device.

公开(公告)号：US20230342186A1

公开(公告)日：2023-10-26

申请号：US17660694

申请日：2022-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Somasundaram Arunachalam

IPC: G06F9/48

CPC classification number: G06F9/4818 ,  G06F9/4881

Abstract: A process includes providing a directed acyclic graph (DAG) that represents an execution order for a plurality of tasks. The DAG includes a plurality of nodes, and each node corresponds to a corresponding task subset of at least one task of the set of tasks. The process includes associating a first priority with a given successor node for the given successor node to execute after a first predecessor node. The given successor node is connected to the first predecessor node by a first edge of the DAG. The process includes associating a second priority with the given successor node for the given successor node to execute after a second predecessor node. The given successor node is connected to the second predecessor node by a second edge of the DAG. The process includes scheduling tasks for execution based on the DAG. The scheduling includes, based on the first and second priority, scheduling the task subset corresponding to the given successor node to execute after the task subset corresponding to the first predecessor node executes; or scheduling the task subset corresponding to the given successor node to execute after the task subset corresponding to the second predecessor node executes.

公开(公告)号：US20230195613A1

公开(公告)日：2023-06-22

申请号：US17644615

申请日：2021-12-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Somasundaram Arunachalam

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1016

Abstract: A technique includes allocating, by a memory manager, a first region of a memory. The allocation includes selecting a logically contiguous first lane of the memory. The first lane is associated with a first identifier. The allocation further includes selecting a logically contiguous second lane of the memory. The second lane is a child of the first lane, and the second lane is orthogonal to the first lane. The second lane is associated with a second identifier. The technique includes, responsive to a request to access the first region, managing, by the memory manager, the access to the first region based on the first identifier and the second identifier.

公开(公告)号：US11099958B2

公开(公告)日：2021-08-24

申请号：US16358638

申请日：2019-03-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Somasundaram Arunachalam

IPC: G06F11/22 ,  G06F9/30 ,  G06F11/14

Abstract: Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.

公开(公告)号：US12299482B2

公开(公告)日：2025-05-13

申请号：US17519058

申请日：2021-11-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Somasundaram Arunachalam

IPC: G06F9/48

Abstract: Approaches for scheduling a set of tasks at compute nodes within a cluster computing environment based on a priority, are described, In an example, a cascaded priority mapping comprising cascaded priority value nodes, wherein the priority value nodes correspond to the set of tasks that are to be scheduled. Each of the priority value nodes specify a priority value attributed to respective tasks from amongst the set of tasks.

公开(公告)号：US12026091B2

公开(公告)日：2024-07-02

申请号：US17644615

申请日：2021-12-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Somasundaram Arunachalam

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1016

Abstract: A technique includes allocating, by a memory manager, a first region of a memory. The allocation includes selecting a logically contiguous first lane of the memory. The first lane is associated with a first identifier. The allocation further includes selecting a logically contiguous second lane of the memory. The second lane is a child of the first lane, and the second lane is orthogonal to the first lane. The second lane is associated with a second identifier. The technique includes, responsive to a request to access the first region, managing, by the memory manager, the access to the first region based on the first identifier and the second identifier.

公开(公告)号：US12265501B1

公开(公告)日：2025-04-01

申请号：US18594413

申请日：2024-03-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Somasundaram Arunachalam

IPC: G06F16/13 ,  G06F16/176 ,  G06F16/18 ,  G06F16/185

Abstract: In certain embodiments, a computer-implemented method includes: receiving, from a user interface and at a planar file system manager executing on one or more processors, a planar file system configuration request comprising a plurality of planes and a plurality of plane relationships, wherein the plurality of plane relationships comprise a sub-planar relationship between a plane and a sub-plane and an orthogonal relationship between two separate planes of the plurality of planes; configuring, by the planar file system manager, a storage environment to include a planar file system based on the planar file system configuration request; receiving, from the user interface, a plane operation request to perform an operation on a plane of the planar file system, wherein the plane operation request comprises a plane identifier corresponding to the plane; and performing, based on the plane operation request, the operation on the plane.

公开(公告)号：US20250045132A1

公开(公告)日：2025-02-06

申请号：US18362696

申请日：2023-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Somasundaram Arunachalam

IPC: G06F9/54

Abstract: In certain embodiments, a method includes providing, by an inter-process communication (IPC) manager, an initial prioritized message access list information set; receiving a second request for at least one prioritized message access list; and providing a prioritized message access list within a shared memory pool. The prioritized message access list may include a prioritized message access list identifier, an intra-list priority range, and a prioritized message access list size. The method may also include parsing, by the IPC manager, a message posted to the prioritized message access list to determine a time at which to alert a receiving process about the message; notifying the receiving process at the determined time; and decrementing, in response to the receiving process consuming the message, a message reference count.

公开(公告)号：US12111757B2

公开(公告)日：2024-10-08

申请号：US17971834

申请日：2022-10-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Somasundaram Arunachalam

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1041

Abstract: Examples of the presently disclosed technology provide new memory management systems and methods that improve dynamic memory region utilization by: (1) creating a new class/type of dynamic memory regions—i.e., “fluid” dynamic memory regions—that are automatically relinquished to a free pool of dynamic memory regions upon expiration of a “fluid memory validity time interval;” and (2) responsive to requests for dynamic memory regions, allocating “fluid” dynamic memory regions when levels of importance for data to be stored in the requested dynamic memory regions fall below a “data-oriented priority-fluidity threshold.”

公开(公告)号：US20200301795A1

公开(公告)日：2020-09-24

申请号：US16358638

申请日：2019-03-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Somasundaram Arunachalam

IPC: G06F11/22 ,  G06F11/14 ,  G06F9/30

Abstract: Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.