公开(公告)号：US09972941B2

公开(公告)日：2018-05-15

申请号：US15106655

申请日：2014-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K Benedict ,  Stephen F Contreras

IPC: H01R12/00 ,  H01R13/6471 ,  H01R12/52 ,  H01R12/72 ,  H01R12/73

CPC classification number: H01R13/6471 ,  H01R12/52 ,  H01R12/721 ,  H01R12/737

Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).

公开(公告)号：US20170005438A1

公开(公告)日：2017-01-05

申请号：US15106655

申请日：2014-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K Benedict ,  Stephen F Contreras

IPC: H01R13/6471 ,  H01R12/73

CPC classification number: H01R13/6471 ,  H01R12/52 ,  H01R12/721 ,  H01R12/737

Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).

Abstract translation: 本文描述了存储器模块连接器（100）。 存储器模块连接器（100）包括分配到多个列（104）中的多个连接器引脚（102）。 多个连接器引脚（102）还包括用于向存储器模块连接器（100）提供电接地的多个接地引脚（106）和用于在存储器模块连接器（100）上承载数据信号的多个信号引脚（108） ）。 此外，对于设置在列（104）中的每个信号引脚（108），与相邻列（104）中的信号引脚（108）相邻的每个连接器引脚（102）是接地引脚（106）。

公开(公告)号：US10453516B2

公开(公告)日：2019-10-22

申请号：US15899514

申请日：2018-02-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M Bacchus ,  Melvin K Benedict ,  Stephen F Contreras ,  Eric L Pope ,  Chi K Sides ,  Chun-Pin Huang

IPC: G11C5/06 ,  G11C5/10 ,  G11C11/4074 ,  G11C5/14 ,  G11C5/04

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.