公开(公告)号：US20230195898A1

公开(公告)日：2023-06-22

申请号：US17923382

申请日：2020-06-24

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： ROSILET RETNAMONI BRADUKE ,  Weize LIU ,  Rajesh A, SHAH

IPC: G06F21/57 ,  G06F9/4401 ,  G06F11/14 ,  H04L9/32

CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F11/1417 ,  G06F21/575 ,  H04L9/3242 ,  H04L9/3247 ,  G06F2201/84 ,  G06F2221/034

Abstract: An example computing device including a processor, a first non-volatile memory to store a first basic input/output system (BIOS) image, a second non- volatile memory, and a controller. The controller Is to receive encrypted location and size information of the first BIOS image from the processor, verify the received encrypted location and size information of the first BIOS image, verify a signature of the first BIOS image in the first non-volatile memory, control a backup process of the first BIOS image to the second non-volatile memory, verify the signature of the backed up first BIOS image in the second non-volatile memory, and in response to a successful verification of the signature, send a message to the processor to cause the processor to perform a boot process using the first BIOS image from the first non-volatile memory.

公开(公告)号：US20200371909A1

公开(公告)日：2020-11-26

申请号：US16755815

申请日：2018-01-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： JEFFREY KEVIN JEANSONNE ,  ROSILET RETNAMONI BRADUKE ,  DAVID PLAQUIN ,  JOSHUA SERRATELLI SCHIFFMAN

IPC: G06F12/02 ,  G06F12/0891 ,  G06F12/0831 ,  G06F12/0853

Abstract: An apparatus includes a solid-state a solid-state non-volatile computer memory; and a controller coupled to the memory. The controller to: generate a data set including a tag that indicates that the data set is valid; write the data set into a block of the memory, wherein the block includes multiple addressable locations set to a common first binary value before the write; generate a subsequent data set including a tag that indicates that the subsequent data set is valid; update the tag of the written data set to indicate that the written data set is invalid, wherein the update includes setting an addressable location corresponding to the tag to second binary value different from the first binary value; write the subsequent data set to addressable locations in the block of memory other than the addressable locations of the invalid data set.