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    ACCESS TO VOLATILE MEMORIES
    1.
    发明公开
    ACCESS TO VOLATILE MEMORIES 审中-公开

    公开(公告)号：US20230359553A1

    公开(公告)日：2023-11-09

    申请号：US18042673

    申请日：2020-10-23

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： MASON GUNYUZLU ,  JEFFREY KEVIN JEANSONNE ,  KHOA HUYNH ,  THOMAS GEORGE SWANN

    IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/18 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F13/18 ,  G06F13/1689 ,  G06F2212/7201

    Abstract: An electronic device is described that may include an integrated circuit, a volatile memory coupled to the integrated circuit, a non-volatile memory controller coupled to the integrated circuit, and a non-volatile memory coupled to the non-volatile memory controller. In some examples, the integrated circuit is to receive a first instruction at a first frequency via a first storage access physical interface and receive a second instruction at a second frequency via a second storage access physical interface, wherein the first instruction and the second instruction are volatile memory access instructions. The integrated circuit may also be to arbitrate access to the volatile memory based on the first instruction and the second instruction and, responsive to the access to the volatile memory, synchronize contents of the volatile memory with the non-volatile memory via the non-volatile memory controller to maintain data coherency between the volatile memory and the non-volatile memory.

    Recovering from Compromised System Boot Code
    4.
    发明申请
    Recovering from Compromised System Boot Code 有权
    从妥协系统引导代码恢复

    公开(公告)号：US20160055068A1

    公开(公告)日：2016-02-25

    申请号：US14780967

    申请日：2013-04-23

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： JEFFREY KEVIN JEANSONNE ,  VALLIUDDIN Y ALI ,  LAN WANG

    IPC: G06F11/14 ,  G06F3/06

    CPC classification number: G06F11/1469 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0683 ,  G06F21/572 ,  G06F2201/84

    Abstract: In a state of a system in which a processor of the system is not accessing a first memory, a controller in the system determines whether system boot code from the first memory in the system is compromised, wherein the first memory is accessible by the processor and the controller over a bus. In response to determining that the system boot code is compromised, the controller retrieves system boot code from a second memory in the computing device to replace the system boot code in the first memory, where the second memory is electrically isolated from the bus and is inaccessible by the processor.

    Abstract translation: 在系统的处理器不访问第一存储器的系统的状态下，系统中的控制器确定来自系统中的第一存储器的系统引导代码是否受到损害，其中第一存储器可由处理器访问，并且 控制器通过总线。 响应于确定系统引导代码被破坏，控制器从计算设备中的第二存储器检索系统引导代码以替换第一存储器中的系统引导代码，其中第二存储器与总线电隔离并且是不可访问的 由处理器。

    ACCESS FILTER FOR BIOS VARIABLES
    5.
    发明申请
    ACCESS FILTER FOR BIOS VARIABLES 有权

    公开(公告)号：US20230026664A1

    公开(公告)日：2023-01-26

    申请号：US17758173

    申请日：2020-01-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： RICHARD CATENA ,  RICHARD ALDEN BRAMLEY, Jr. ,  JEFFREY KEVIN JEANSONNE

    IPC: G06F21/57 ,  G06F21/56

    Abstract: An example computing device includes: a storage device; a first controller to retrieve basic input/output system (BIOS) instructions, including a set of filter criteria, from the storage device, and execute the BIOS instructions to: detect a command to change a set of BIOS variables associated with the BIOS instructions; store the command in a log; compare a payload of the command with the set of filter criteria; and accept or reject the change to the set of BIOS variables according to the comparison.

    PERIPHERAL DEVICE CONFIGURATIONS BY HOST SYSTEMS
    6.
    发明申请
    PERIPHERAL DEVICE CONFIGURATIONS BY HOST SYSTEMS 有权

    公开(公告)号：US20210405718A1

    公开(公告)日：2021-12-30

    申请号：US16641904

    申请日：2017-11-17

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： ISAAC LAGNADO ,  STEVEN PETIT ,  LEE E. LEPPO ,  JEFFREY KEVIN JEANSONNE ,  ROGER D. BENSON

    IPC: G06F1/26 ,  G06F13/10

    Abstract: An apparatus including a host system is provided. The apparatus includes a peripheral device in communication with the host system. The apparatus also includes a programmable memory unit within the peripheral device. The programmable memory unit is to receive a configuration profile from the host system. The configuration profile is to re-configure as an embedded device. In addition, the apparatus includes a power delivery system to provide power to the programmable memory unit and to provide power to an accessory of the peripheral device separately. The power delivery system provides power to the programmable memory unit to allow re-configuration of the peripheral device as the embedded device.

    Repairing Compromised System Data in a Non-Volatile Memory
    7.
    发明申请
    Repairing Compromised System Data in a Non-Volatile Memory 有权
    在非易失性存储器中修复被破坏的系统数据

    公开(公告)号：US20160055069A1

    公开(公告)日：2016-02-25

    申请号：US14780981

    申请日：2013-04-23

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： JEFFREY KEVIN JEANSONNE ,  VALIUDDIN Y ALI ,  BORIS BALACHEFF

    IPC: G06F11/14 ,  G06F3/06

    CPC classification number: G06F11/1469 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0683 ,  G06F11/1417 ,  G06F11/1456 ,  G06F11/1458 ,  G06F11/1612 ,  G06F2201/83 ,  G06F2201/84

    Abstract: A first non-volatile memory stores a redundant copy of system data that relates to a configuration of at least one physical component of a system, where the first non-volatile memory is accessible by a controller in the system and inaccessible to a processor in the system. It is determined whether system data in a second non-volatile memory accessible by the processor is compromised. In response to determining that the system data in the second non-volatile memory is compromised, the compromised system data in the second non-volatile memory is repaired.

    Abstract translation: 第一非易失性存储器存储与系统的至少一个物理组件的配置相关的系统数据的冗余副本，其中第一非易失性存储器可由系统中的控制器访问，并且在处理器中不可访问 系统。 确定处理器可访问的第二非易失性存储器中的系统数据是否受到损害。 响应于确定第二非易失性存储器中的系统数据被破坏，第二非易失性存储器中受损的系统数据被修复。

    CONFIGURATION DATA DELETION BASED ON TAMPER STATUS
    8.
    发明申请
    CONFIGURATION DATA DELETION BASED ON TAMPER STATUS 有权

    公开(公告)号：US20220391545A1

    公开(公告)日：2022-12-08

    申请号：US17341448

    申请日：2021-06-08

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： CHRISTOPHER HOWARD STEWART ,  JEFFREY KEVIN JEANSONNE ,  RICHARD ALDEN BRAMLEY, JR. ,  MAUGAN CEDRIC VILLATEL

    IPC: G06F21/78 ,  G06F21/60 ,  G06F21/31 ,  G06F3/06

    Abstract: An example storage medium includes instructions that, when executed, cause a processor of a computing device to read, during start-up of the computing device, first configuration data from a first storage device of the computing device; read second configuration data from a second storage device of the computing device; determine that there is an inconsistency between the first configuration data and the second configuration data; check a tamper status of the computing device; based on the tamper status and the determination that there is an inconsistency between the first configuration data and the second configuration data: (i) clear a secure storage location of the computing device, the secure storage location storing data to access protected data; or (ii) replace the first configuration data on the first storage device of the computing device based on second data and continue the start-up of the computing device.

    VALIDITY OF DATA SETS STORED IN MEMORY
    9.
    发明申请
    VALIDITY OF DATA SETS STORED IN MEMORY 审中-公开

    公开(公告)号：US20200371909A1

    公开(公告)日：2020-11-26

    申请号：US16755815

    申请日：2018-01-29

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： JEFFREY KEVIN JEANSONNE ,  ROSILET RETNAMONI BRADUKE ,  DAVID PLAQUIN ,  JOSHUA SERRATELLI SCHIFFMAN

    IPC: G06F12/02 ,  G06F12/0891 ,  G06F12/0831 ,  G06F12/0853

    Abstract: An apparatus includes a solid-state a solid-state non-volatile computer memory; and a controller coupled to the memory. The controller to: generate a data set including a tag that indicates that the data set is valid; write the data set into a block of the memory, wherein the block includes multiple addressable locations set to a common first binary value before the write; generate a subsequent data set including a tag that indicates that the subsequent data set is valid; update the tag of the written data set to indicate that the written data set is invalid, wherein the update includes setting an addressable location corresponding to the tag to second binary value different from the first binary value; write the subsequent data set to addressable locations in the block of memory other than the addressable locations of the invalid data set.

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