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公开(公告)号：US08051331B2
公开(公告)日：2011-11-01
申请号：US12412117
申请日：2009-03-26
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US20090187703A1
公开(公告)日：2009-07-23
申请号：US12412117
申请日：2009-03-26
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US20080059852A1
公开(公告)日：2008-03-06
申请号：US11877500
申请日：2007-10-23
IPC分类号： G11C29/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较 数据。 ROM1a的FD1＆lt; 2＆gt ;. 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US07549086B2
公开(公告)日：2009-06-16
申请号：US11877500
申请日：2007-10-23
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US07305589B2
公开(公告)日：2007-12-04
申请号：US10484043
申请日：2002-05-08
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较 ROM4a的数据FD1 <2> 。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US20070033334A1
公开(公告)日：2007-02-08
申请号：US11541543
申请日：2006-10-03
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
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公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
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公开(公告)号：US07133961B2
公开(公告)日：2006-11-07
申请号：US10195400
申请日：2002-07-16
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
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公开(公告)号：US06917547B2
公开(公告)日：2005-07-12
申请号：US10616955
申请日：2003-07-11
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
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公开(公告)号：US07403436B2
公开(公告)日：2008-07-22
申请号：US11453926
申请日：2006-06-16
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
摘要翻译： 当在包含非易失性存储器和纠错电路的卡存储装置中发生非易失性存储器写入错误时，从非易失性存储器读取写入数据，并且检查错误是否可以通过错误来校正 校正电路。 如果可以纠正错误，则写入操作结束。 如果纠错电路无法纠正错误，则执行替代处理以将数据写入其他区域。
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