公开(公告)号：US20180047855A1

公开(公告)日：2018-02-15

申请号：US15558130

申请日：2015-05-15

Applicant: HITACHI, LTD.

Inventor： Kan YASUI ,  Hiroyuki MATSUSHIMA ,  Hiroyuki OKINO

IPC: H01L29/872 ,  H01L29/06 ,  H01L25/18 ,  H01L29/16

Abstract: In a Schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first Schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first Schottky junction and connected to the first electrode; at the border of the active region and a periphery region, a second Schottky junction comprising the first electrode and the first semiconductor region and having at least one annular pattern surrounding the linear patterns is provided and the second semiconductor region is adjacent to the second Schottky junction and is connected to the first electrode; and the first and second Schottky junctions are conductive parts and the second semiconductor region is a nonconductive part in a forward bias state.

公开(公告)号：US20150318389A1

公开(公告)日：2015-11-05

申请号：US14651555

申请日：2012-12-28

Applicant: HITACHI, LTD.

Inventor： Ryuta TSUCHIYA ,  Hiroyuki MATSUSHIMA ,  Naoki TEGA ,  Digh HISAMOTO

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/02529 ,  H01L21/0485 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7813

Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

Abstract translation: 为了降低SiC DOMSFET中的导通电阻而减小栅极长度，难以同时通过栅极长度的降低和高的元件耐受电压来实现导通电阻的降低。 在本发明中，在形成源极扩散层区域之后形成体层，然后使源极扩散层区域的一部分凹陷。 由于体层的存在，可以增大源极扩散区域和各个端部之间的距离，有效地扩大耗尽层，并且可以抑制端部的电场浓度，从而提高耐电压特性。 因此，本发明可以提供通过同时降低栅极长度和高元件耐受电压来实现沟道电阻降低的碳化硅半导体器件。