公开(公告)号：US20160085463A1

公开(公告)日：2016-03-24

申请号：US14492107

申请日：2014-09-22

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Akira FUJIBAYASHI ,  Mutsumi HOSOYA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0676 ,  G06F3/0689 ,  H04L49/357 ,  H04L67/1002 ,  H04L67/1097 ,  H04L69/08

Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.

公开(公告)号：US20240361940A1

公开(公告)日：2024-10-31

申请号：US18469063

申请日：2023-09-18

Applicant: Hitachi, Ltd.

Inventor： Mutsumi HOSOYA ,  Tomohiro YOSHIHARA ,  Yoshinori OHIRA ,  Norio SHIMOZONO

IPC: G06F3/06

CPC classification number: G06F3/0646 ,  G06F3/0608 ,  G06F3/067

Abstract: A processor of a storage system calculates long-term load fluctuation prediction as a prediction of load fluctuation over time in the future of the controller nodes based on time-series data of load of the controller nodes. The processor calculates an addition/reduction completion target time to complete addition or reduction of an operating controller node out of the controller nodes based on the long-term load fluctuation prediction and a load threshold value determined from a power performance model. The processor calculates a rebalancing time for a rebalancing process based on data movement in the rebalancing process for moving data between the drive nodes in accordance with the addition or the reduction and bandwidth information of a path for the data movement. The processor calculates a start time of the rebalancing process from the addition/reduction completion target time and the rebalancing time and starts the rebalancing process at the start time.

公开(公告)号：US20160196077A9

公开(公告)日：2016-07-07

申请号：US14492107

申请日：2014-09-22

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Akira FUJIBAYASHI ,  Mutsumi HOSOYA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0676 ,  G06F3/0689 ,  H04L49/357 ,  H04L67/1002 ,  H04L67/1097 ,  H04L69/08

Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.

Abstract translation: 存储系统：其中处理器号信息包括至少一个逻辑单元号和至少一个处理器数量的存储节点; 其中传送列表索引/处理器号信息包括用于从多个存储节点的处理器中识别处理器的处理器号，以及用于识别包括处理器发送给协议处理器的指令的传送列表的索引信息; 其中本地路由器响应于来自主计算机的协议处理器的写入请求，基于处理器号信息从多个存储节点的处理器中确定作为写请求的传送目的地的第一处理器; 其中所述第一处理器生成并向所述协议处理器发送包括用于处理的指令的第一传送列表，并且在接收到所述写入请求时生成作为所述第一传送列表的索引的第一索引信息。

公开(公告)号：US20250147883A1

公开(公告)日：2025-05-08

申请号：US18592777

申请日：2024-03-01

Applicant: Hitachi, Ltd.

Inventor： Mutsumi HOSOYA ,  Norio SHIMOZONO

IPC: G06F12/0802

Abstract: One object of the disclosure is to reduce a capacity of cached data, reduce a transfer volume, or reduce a management cost. One aspect of the disclosure is a computer system including a storage control unit and a storage apparatus. The storage control unit receives a notification of information on an operation mode determined by an operation mode determination unit based on processing executed by a processing execution unit. When an access request is received via a virtual volume from the processing execution unit in a case where target data is not stored in a cache volume, the storage control unit executes an access to a real volume. The storage control unit controls the cache volume based on the information on the operation mode.

公开(公告)号：US20190095651A1

公开(公告)日：2019-03-28

申请号：US16082259

申请日：2016-07-07

Applicant: Hitachi, Ltd

Inventor： Nobuhiro YOKOI ,  Mutsumi HOSOYA ,  Ken SUGIMOTO

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G06F3/06

Abstract: A computer system includes a processor, a volatile storage device that stores a program to be executed by the processor, and a plurality of nonvolatile storage devices that store data. Each of the plurality of nonvolatile storage devices holds a first encryption key for encrypting and decrypting first data. Each nonvolatile storage device in the plurality of nonvolatile storage devices transfers the first data to another nonvolatile storage device in the plurality of nonvolatile storage devices in an encrypted or unencrypted state determined according to a predetermined rule.

公开(公告)号：US20150350301A1

公开(公告)日：2015-12-03

申请号：US14813232

申请日：2015-07-30

Applicant: HITACHI, LTD.

Inventor： Nobuhiro YOKOI ,  Mutsumi HOSOYA ,  Nagamasa MIZUSHIMA ,  Yoshihiro YOSHII ,  Masabumi SHIBATA

IPC: H04L29/08 ,  H04L29/06

CPC classification number: H04L67/06 ,  G06F3/06 ,  G06F12/1081 ,  G06F15/17331 ,  H04L67/1097 ,  H04L67/42

Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.

Abstract translation: 有效降低了服务器与存储器之间的传输数据量，实现了服务器与存储之间的有效带宽。 接口设备位于服务器模块中，并且当接收到由服务器处理器发出的读取请求时，将读取的请求发送到存储处理器。 在从存储处理器接收到通过转换被读取请求的对象数据而获取的转换后对象数据进行反向转换的反向转换指令的DMA来传送存储在存储器中的转换后对象数据 执行在存储存储器上的转移源地址到服务器存储器上的传送目的地地址，同时反转转换后转换对象数据。

公开(公告)号：US20150143002A1

公开(公告)日：2015-05-21

申请号：US14608442

申请日：2015-01-29

Applicant: HITACHI, LTD.

Inventor： Nobuhiro YOKOI ,  Mutsumi HOSOYA ,  Kazushi NAKAGAWA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0613 ,  G06F3/067 ,  G06F13/28

Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.

Abstract translation: 计算机系统包括第一存储控制模块和至少一个服务器模块。 第一存储控制模块包括多个存储处理器。 每个服务器模块包括服务器处理器和连接到服务器处理器的服务器I / F和多个存储处理器中的至少两个。 作为至少一个服务器模块中的任一个的发行服务器的服务器I / F通过参照其中由服务器处理器发出的I / O请求的发布服务器的识别信息的排序信息来指定存储处理器 发布服务器，I / O请求的目的地存储区域的识别信息和负责目的地存储区域的存储处理器的识别信息相互关联，并且将基于I / O请求的命令发送到 指定的存储处理器。