公开(公告)号：US20160254803A1

公开(公告)日：2016-09-01

申请号：US15028568

申请日：2013-10-16

Applicant: HITACHI, LTD.

Inventor： Yusuke KANNO ,  Takeshi SAKATA ,  Nobuyasu KANEKAWA

IPC: H03K3/037 ,  H03K3/3562

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/0948 ,  H03K19/17724 ,  H03K19/17728 ,  H03K19/20 ,  H03K19/23

Abstract: Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.

Abstract translation: 提供了能够减少与确保可靠性相关联的惩罚的半导体器件。 半导体器件包括具有彼此独立的三个系统或更多个输入/输出路径的锁存电路。 锁存电路包括分别设置在三个或更多个系统的输入/输出路径上的多个存储元件STE1至STE3，并且与时钟信号同步地保持输入数据。 多个存储元件STE1至STE3中的至少一个存储元件（例如，STE1）包括使用来自不同于其它输入/输出路径的其他输入/输出路径上提供的存储元件的数据执行多数决定的多数决定单元（例如，81a） 其输入/输出路径并输出反映多数决定结果的数据。

公开(公告)号：US20180260687A1

公开(公告)日：2018-09-13

申请号：US15761217

申请日：2016-04-26

Applicant: Hitachi, Ltd.

Inventor： Yusuke KANNO ,  Takeshi SAKATA ,  Shigeru NAKAHARA

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0454 ,  G06N3/063 ,  G06N3/08

Abstract: Efficient learning of a neural network can be performed. A plurality of DNNs are hierarchically configured, and data of a hidden layer of a DNN of a first hierarchy machine learning/recognizing device is used as input data of a DNN of a second hierarchy machine learning/recognizing device.