公开(公告)号：US20160149025A1

公开(公告)日：2016-05-26

申请号：US14904685

申请日：2013-07-16

Applicant: HITACHI LTD.

Inventor： Yuki MORI ,  Toshiyuki MINE ,  Hiroshi MIKI ,  Mieko MATSUMURA ,  HIrotaka HAMAMURA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/7802 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66068

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract translation: 提供了一种在半导体器件中与Si功率MOSFET一样多地确保栅极绝缘膜的可靠性的技术，其中使用具有比硅更大的带隙的半导体材料，并且其典型例如为 一个SiC功率MOSFET。 为了实现该目的，在SiC功率MOSFET中，栅电极GE形成为与栅极绝缘膜GOX接触，并且由厚度等于或小于200nm的多晶硅膜PF1形成， 和形成为与多晶硅膜PF1接触并且具有任何厚度的多晶硅膜PF2。