公开(公告)号：US20160111499A1

公开(公告)日：2016-04-21

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh HISAMOTO ,  Keisuke KOBAYASHI ,  Naoki TEGA ,  Toshiyuki OHNO ,  Hirotaka HAMAMURA ,  Mieko MATSUMURA

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/045 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/872

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract translation: 使用SiC衬底的MOSFET具有通过由于热氧化施加机械应力而在表面上形成碳过量层的问题，并且碳过量层降低沟道载流子的迁移率。 在本发明中，（1）除去含有碳 - 碳键的层; （2）通过沉积方法形成栅极绝缘膜; 和（3）晶体表面和绝缘膜之间的界面在短时间内在低温下进行界面处理。 由此，有效地消除了引起特性劣化的碳过量层，同时通过使氧化膜和氧氮化物膜进行界面处理，可以有效地消除悬挂键。

公开(公告)号：US20180090574A1

公开(公告)日：2018-03-29

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko MATSUMURA ,  Junichi SAKANO ,  Naoki TEGA ,  Yuki MORI ,  Haruka SHIMIZU ,  Keisuke KOBAYASHI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L29/0615 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

公开(公告)号：US20160149025A1

公开(公告)日：2016-05-26

申请号：US14904685

申请日：2013-07-16

Applicant: HITACHI LTD.

Inventor： Yuki MORI ,  Toshiyuki MINE ,  Hiroshi MIKI ,  Mieko MATSUMURA ,  HIrotaka HAMAMURA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/7802 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66068

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract translation: 提供了一种在半导体器件中与Si功率MOSFET一样多地确保栅极绝缘膜的可靠性的技术，其中使用具有比硅更大的带隙的半导体材料，并且其典型例如为 一个SiC功率MOSFET。 为了实现该目的，在SiC功率MOSFET中，栅电极GE形成为与栅极绝缘膜GOX接触，并且由厚度等于或小于200nm的多晶硅膜PF1形成， 和形成为与多晶硅膜PF1接触并且具有任何厚度的多晶硅膜PF2。