公开(公告)号：US20230139599A1

公开(公告)日：2023-05-04

申请号：US18146996

申请日：2022-12-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Zhengbo Wang ,  Jingjie Cui

IPC: G06F3/06

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.

公开(公告)号：US12014058B2

公开(公告)日：2024-06-18

申请号：US18146996

申请日：2022-12-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Zhengbo Wang ,  Jingjie Cui

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0685 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.