公开(公告)号：US20240172450A1

公开(公告)日：2024-05-23

申请号：US18421986

申请日：2024-01-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Kailiang Huang ,  Junxiao Feng ,  Zhengbo Wang

IPC: H10B53/30 ,  H01L21/28 ,  H01L29/423 ,  H10B53/10 ,  H10B53/20 ,  H10B53/40

CPC classification number: H10B53/30 ,  H01L29/40111 ,  H01L29/42392 ,  H10B53/10 ,  H10B53/20 ,  H10B53/40

Abstract: A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.

公开(公告)号：US12014058B2

公开(公告)日：2024-06-18

申请号：US18146996

申请日：2022-12-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Zhengbo Wang ,  Jingjie Cui

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0685 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.

公开(公告)号：US20230371229A1

公开(公告)日：2023-11-16

申请号：US18358434

申请日：2023-07-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Weiliang Jing ,  Kailiang Huang ,  Junxiao Feng ,  Zhengbo Wang

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A thin-film transistor (TFT) includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate.

公开(公告)号：US20240259022A1

公开(公告)日：2024-08-01

申请号：US18628805

申请日：2024-04-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ying Wu ,  Weiliang Jing ,  Zhaozhao Hou ,  Renshi Fan ,  JEFFREY JUNHAO XU

IPC: H03K19/0944 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20 ,  H03K3/037

Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.

公开(公告)号：US20240121942A1

公开(公告)日：2024-04-11

申请号：US18542615

申请日：2023-12-16

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Kailiang Huang ,  Junxiao Feng ,  Zhengbo Wang

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: A memory comprises a substrate and a plurality of storage units formed on the substrate. Each of the storage units includes a transistor and a capacitor electrically connected to the transistor. The transistor includes a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. The first electrode and the second electrode are arranged in a first direction. The gate is located between the first electrode and the second electrode. The semiconductor layer is located on one of two opposite sides of the gate in a second direction. The semiconductor layer is electrically connected separately to the first electrode and the second electrode, the gate and the semiconductor layer are isolated from each other by the gate dielectric layer, and the second direction is a direction parallel to the substrate.

公开(公告)号：US20230139599A1

公开(公告)日：2023-05-04

申请号：US18146996

申请日：2022-12-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Zhengbo Wang ,  Jingjie Cui

IPC: G06F3/06

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.