公开(公告)号：US20200066331A1

公开(公告)日：2020-02-27

申请号：US16600034

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US20230152977A1

公开(公告)日：2023-05-18

申请号：US18154532

申请日：2023-01-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Chuanzeng Liang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory management technology may be applied to a computer system including a dynamic random-access (DRAM). According to the memory management technology, a corresponding row management policy may be executed based on an access type of memory access, where the access type of the memory access includes a read access or a write access.

公开(公告)号：US11705180B2

公开(公告)日：2023-07-18

申请号：US17370755

申请日：2021-07-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

CPC classification number: G11C11/40618

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US11074958B2

公开(公告)日：2021-07-27

申请号：US16600034

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C16/04 ,  G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US20250094366A1

公开(公告)日：2025-03-20

申请号：US18889766

申请日：2024-09-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhenjun Liu ,  Chuanzeng Liang ,  Erqing Qian ,  Biwei He

IPC: G06F13/16 ,  G06F11/30

Abstract: A page status management method includes collecting statistics on N first memory access commands received in a first time window; determining reception interval information of the N first memory access commands, where the reception interval information indicates denseness of a stream of commands in the first time window; determining active standby time based on the reception interval information; and after a second memory access command accesses a target memory page, if no other memory access command accesses the target memory page within the active standby time, closing the target memory page, where the second memory access command is any memory access command received in a second time window, and the second time window is a time window after the first time window.

公开(公告)号：US20210335417A1

公开(公告)日：2021-10-28

申请号：US17370755

申请日：2021-07-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US20200066330A1

公开(公告)日：2020-02-27

申请号：US16599980

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a memory controller and a dynamic random access memory (DRAM). The memory controller receives access requests including access requests for accessing a first rank of multiple ranks in the DRAM. When a quantity of the access requests for accessing the first rank is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. The first rank may be refreshed in time even if the first rank cannot be in an idle state.