公开(公告)号：US12100448B2

公开(公告)日：2024-09-24

申请号：US17530128

申请日：2021-11-18

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin Gao ,  Kanwen Wang ,  Junren Chen ,  Rui Zhang ,  Huaqiang Wu

IPC: G11C13/00 ,  G06N3/065

CPC classification number: G11C13/0069 ,  G06N3/065 ,  G11C2013/0078 ,  G11C2213/15

Abstract: A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

公开(公告)号：US20220262435A1

公开(公告)日：2022-08-18

申请号：US17733233

申请日：2022-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jianxing Liao ,  Wei Wu ,  Leibin Ni ,  Kanwen Wang ,  Rui Zhang

IPC: G11C13/00

Abstract: This application provides a unit, including a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are connected to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be connected and disconnected; the resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor; where the resistance of the memristor is used to indicate the first data stored by the memristor; and when a voltage used to indicate second data is input to a second electrode of the first transistor which is configured to output a computation result of the first data and the second data from a third electrode of the first transistor.

公开(公告)号：US11705180B2

公开(公告)日：2023-07-18

申请号：US17370755

申请日：2021-07-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

CPC classification number: G11C11/40618

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US11074958B2

公开(公告)日：2021-07-27

申请号：US16600034

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C16/04 ,  G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US11232031B2

公开(公告)日：2022-01-25

申请号：US16419260

申请日：2019-05-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Xing Hu ,  Kanwen Wang ,  Wei Yang

IPC: G06F12/06 ,  G06F12/10 ,  G06F12/02

Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

公开(公告)号：US20200066331A1

公开(公告)日：2020-02-27

申请号：US16600034

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US20190272230A1

公开(公告)日：2019-09-05

申请号：US16419260

申请日：2019-05-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Xing Hu ,  Kanwen Wang ,  Wei Yang

IPC: G06F12/06 ,  G06F12/10

Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

公开(公告)号：US20240013037A1

公开(公告)日：2024-01-11

申请号：US18475262

申请日：2023-09-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ziyang Zhang ,  Tao Liu ,  Kanwen Wang ,  Jianxing Liao

IPC: G06N3/049

CPC classification number: G06N3/049

Abstract: A spiking neural network circuit implemented in a chip includes a plurality of decompression modules and a calculation module. The plurality of decompression modules are configured to obtain a plurality of weight values in a compressed weight matrix and identifiers of a plurality of corresponding output neurons based on information about a plurality of input neurons. Each of the plurality of decompression modules is configured to obtain weight values with a same row number in the compressed weight matrix and identifiers of a plurality of output neurons corresponding to the weight values with the same row number. Each row of the compressed weight matrix has a same quantity of non-zero weight values. Each row of weight values corresponds to one input neuron. The calculation module then determines corresponding membrane voltages of the plurality of output neurons based on the plurality of weight values.

公开(公告)号：US20210335417A1

公开(公告)日：2021-10-28

申请号：US17370755

申请日：2021-07-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

公开(公告)号：US20200066330A1

公开(公告)日：2020-02-27

申请号：US16599980

申请日：2019-10-11

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Xing Hu ,  Chuanzeng Liang ,  Shihai Xiao ,  Kanwen Wang

IPC: G11C11/406

Abstract: A memory refresh method is applied to a computer system including a memory controller and a dynamic random access memory (DRAM). The memory controller receives access requests including access requests for accessing a first rank of multiple ranks in the DRAM. When a quantity of the access requests for accessing the first rank is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. The first rank may be refreshed in time even if the first rank cannot be in an idle state.