PICTURE SELECTION METHOD AND RELATED DEVICE

    公开(公告)号:US20210281754A1

    公开(公告)日:2021-09-09

    申请号:US17330133

    申请日:2021-05-25

    Abstract: In a method for selecting pictures from a sequence of pictures of an object in motion, a computerized user device determines, for each picture in the sequence of pictures, a value of a motion feature of the object. Based on analyzing the values of the motion feature of the pictures in the sequence, the device identifies a first subset of pictures from the pictures in the sequence. The device then selects, based on a second selection criterion, a second subset of pictures from the first subset of pictures. The pictures in the second subset are displayed to a user for further selection.

    Memory access processing method, apparatus, and system

    公开(公告)号:US09898206B2

    公开(公告)日:2018-02-20

    申请号:US15017081

    申请日:2016-02-05

    CPC classification number: G06F3/0611 G06F3/0656 G06F3/0683 G06F9/3824

    Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

    Method and system for generating accelerator program

    公开(公告)号:US10372429B2

    公开(公告)日:2019-08-06

    申请号:US15988225

    申请日:2018-05-24

    Abstract: A method for generating an accelerator program is disclosed, to help increase utilization of an accelerator and increase program development efficiency. In some feasible implementations of the present invention, the method includes: obtaining an accelerator program description that is based on a state machine, where the accelerator program description includes multiple state machines separately configured to implement an application program, and the multiple state machines form a pipeline according to a data dependency in a directed acyclic graph DAG corresponding to the application program; and performing state machine splicing on the state machines in the accelerator program description by using an accelerator compilation tool, to generate an accelerator program.

    Method, apparatus, and chip for implementing mutually-exclusive operation of multiple threads

    公开(公告)号:US10331499B2

    公开(公告)日:2019-06-25

    申请号:US15686830

    申请日:2017-08-25

    Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

    METHOD AND SYSTEM FOR GENERATING ACCELERATOR PROGRAM

    公开(公告)号:US20180267784A1

    公开(公告)日:2018-09-20

    申请号:US15988225

    申请日:2018-05-24

    CPC classification number: G06F8/433 G06F8/42 G06F8/4452 G06F9/4498

    Abstract: A method for generating an accelerator program is disclosed, to help increase utilization of an accelerator and increase program development efficiency. In some feasible implementations of the present invention, the method includes: obtaining an accelerator program description that is based on a state machine, where the accelerator program description includes multiple state machines separately configured to implement an application program, and the multiple state machines form a pipeline according to a data dependency in a directed acyclic graph DAG corresponding to the application program; and performing state machine splicing on the state machines in the accelerator program description by using an accelerator compilation tool, to generate an accelerator program.

    Image denoising method and apparatus

    公开(公告)号:US12062158B2

    公开(公告)日:2024-08-13

    申请号:US17462176

    申请日:2021-08-31

    CPC classification number: G06T5/70 G06N3/045 G06T5/50

    Abstract: This application provides an image denoising method and apparatus, and relates to the artificial intelligence field and specifically relates to the computer vision field. The method includes: performing resolution reduction processing on a to-be-processed image to obtain a plurality of images whose resolutions are lower than that of the to-be-processed image; extracting an image feature of a higher-resolution image based on an image feature of a lower-resolution image to obtain an image feature of the to-be-processed image; and performing denoising processing on the to-be-processed image based on the image feature of the to-be-processed image to obtain a denoised image. This application can improve an image denoising effect.

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