公开(公告)号：US09483321B2

公开(公告)日：2016-11-01

申请号：US14676195

申请日：2015-04-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuanchao Xu ,  Dongrui Fan ,  Hao Zhang ,  Xiaochun Ye

IPC: G06F9/46 ,  G06F13/00 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5088 ,  G06F9/4881

Abstract: A method and an apparatus for determining a to-be-migrated task based on cache awareness in a computing system having multiple processor cores is disclosed. In the method, the computing system determines a source processor core and a destination processor core according to a load of each processor core. Through respectively monitoring the number of cache misses of each task and the number of executed instructions of each task in the source processor core and the destination processor core, the computing system obtain an average cache miss per kilo instructions of the source processor core and an average cache miss per kilo instructions of the destination processor core. Then, the computing system determines, according to the obtained average cache miss per kilo instructions of the source processor core and the destination processor core, a task to be migrated from the source processor core to the destination processor core.

Abstract translation: 公开了一种在具有多个处理器核心的计算系统中基于缓存感知来确定待迁移任务的方法和装置。 在该方法中，计算系统根据每个处理器核心的负载来确定源处理器核心和目标处理器核心。 通过分别监视每个任务的高速缓存未命中的数量和源处理器核心和目标处理器核心中的每个任务的执行指令的数量，计算系统获得源处理器核心的每千个指令的平均高速缓存未命中，并且平均 目标处理器核心的每千克缓存命中指示。 然后，计算系统根据获得的源处理器核心和目标处理器核心的每千指令的平均高速缓存未命中确定要从源处理器核心迁移到目标处理器核心的任务。

公开(公告)号：US20150205642A1

公开(公告)日：2015-07-23

申请号：US14676195

申请日：2015-04-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuanchao Xu ,  Dongrui Fan ,  Hao Zhang ,  Xiaochun Ye

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5088 ,  G06F9/4881

Abstract: A method and an apparatus for determining a to-be-migrated task based on cache awareness in a computing system having multiple processor cores is disclosed. In the method, the computing system determines a source processor core and a destination processor core according to a load of each processor core. Through respectively monitoring the number of cache misses of each task and the number of executed instructions of each task in the source processor core and the destination processor core, the computing system obtain an average cache miss per kilo instructions of the source processor core and an average cache miss per kilo instructions of the destination processor core. Then, the computing system determines, according to the obtained average cache miss per kilo instructions of the source processor core and the destination processor core, a task to be migrated from the source processor core to the destination processor core.

Abstract translation: 公开了一种在具有多个处理器核心的计算系统中基于缓存感知来确定待迁移任务的方法和装置。 在该方法中，计算系统根据每个处理器核心的负载来确定源处理器核心和目标处理器核心。 通过分别监视每个任务的高速缓存未命中的数量和源处理器核心和目标处理器核心中的每个任务的执行指令的数量，计算系统获得源处理器核心的每千个指令的平均高速缓存未命中，并且平均 目标处理器核心的每千克缓存命中指示。 然后，计算系统根据获得的源处理器核心和目标处理器核心的每千指令的平均高速缓存未命中确定要从源处理器核心迁移到目标处理器核心的任务。

公开(公告)号：US09880937B2

公开(公告)日：2018-01-30

申请号：US14328173

申请日：2014-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lingjun Fan ,  Shibin Tang ,  Da Wang ,  Hao Zhang ,  Dongrui Fan

IPC: G06F12/08 ,  G06F1/32 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0831 ,  G06F12/0891

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/0895 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/621 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.

公开(公告)号：US20160154590A1

公开(公告)日：2016-06-02

申请号：US15017081

申请日：2016-02-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Dongrui Fan ,  Fenglong Song ,  Da Wang ,  Xiaochun Ye

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3824

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

Abstract translation: 存储器访问处理方法和装置以及系统。 该方法包括接收由处理器发送的存储器访问请求，组合在预设时间段内接收到的多个存储器访问请求以形成新的存储器访问请求，其中新的存储器访问请求包括与存储器地址相对应的代码位向量。 第一码位标识符被配置用于处于码位向量中并对应于由多个存储器访问请求访问的存储器地址的码位。 该方法还包括将新的存储器访问请求发送到存储器控制器，使得存储器控制器对与第一代码位标识符相对应的存储器地址执行存储器访问操作。 该方法有效地提高了内存带宽利用率。

公开(公告)号：US09990229B2

公开(公告)日：2018-06-05

申请号：US14730425

申请日：2015-06-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Dongrui Fan ,  Xiaochun Ye ,  Da Wang ,  Hao Zhang

IPC: G06F9/48 ,  G06F3/12 ,  G06F9/50

CPC classification number: G06F9/4887 ,  G06F3/126 ,  G06F9/4881 ,  G06F9/5038

Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.

公开(公告)号：US09898206B2

公开(公告)日：2018-02-20

申请号：US15017081

申请日：2016-02-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Dongrui Fan ,  Fenglong Song ,  Da Wang ,  Xiaochun Ye

IPC: G06F3/06 ,  G06F9/38

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3824

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

公开(公告)号：US20150268996A1

公开(公告)日：2015-09-24

申请号：US14730425

申请日：2015-06-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Dongrui Fan ,  Xiaochun Ye ,  Da Wang ,  Hao Zhang

IPC: G06F9/48

CPC classification number: G06F9/4887 ,  G06F3/126 ,  G06F9/4881 ,  G06F9/5038

Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.

Abstract translation: 公开了一种用于在计算系统中动态调度多个任务的实时多任务调度方法和装置。 在该方法中，计算系统的处理器确定应对当前调度的任务执行松弛度校正，然后根据当前调度任务的执行进度获取当前调度任务的剩余执行时间， 当前计划的任务已执行。 根据当前调度任务的剩余执行时间和当前调度任务的最后期限获取当前调度任务的松弛度后，处理器根据当前调度任务的松弛度来确定当前调度任务的优先级，以及 根据任务的优先级重新确定优先级队列。 然后，处理器根据重新确定的优先级队列调度多个任务。

公开(公告)号：US20140344522A1

公开(公告)日：2014-11-20

申请号：US14328173

申请日：2014-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lingjun Fan ,  Shibin Tang ,  Da Wang ,  Hao Zhang ,  Dongrui Fan

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/0895 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/621 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.

Abstract translation: 本发明提供了一种用于处理器的动态组关联高速缓存装置。 当读取访问发生时，设备首先确定要访问的高速缓存集中的每个高速缓存块的有效/无效位，并根据每个高速缓存块的有效/无效位设置缓存方式的使能/禁止位 其中高速缓存块位于其中; 然后，读取有效的高速缓存块，将存储器地址中的标签部分与读取的每个高速缓存块中的标签块进行比较，并且如果存在命中，则根据偏移部分从命中高速缓存块中的数据块读取数据 的内存地址。