PACKET BACKPRESSURE DETECTION METHOD, APPARATUS, AND DEVICE

    公开(公告)号:US20200042425A1

    公开(公告)日:2020-02-06

    申请号:US16653326

    申请日:2019-10-15

    Abstract: A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

    Method and system for upgrading a firmware of a chip and baseboard management controller by waiting until an idle state of a connected system to finish upgrade
    2.
    发明授权
    Method and system for upgrading a firmware of a chip and baseboard management controller by waiting until an idle state of a connected system to finish upgrade 有权
    通过等待连接系统的空闲状态完成升级来升级芯片和基板管理控制器的固件的方法和系统

    公开(公告)号:US09152544B2

    公开(公告)日:2015-10-06

    申请号:US13689246

    申请日:2012-11-29

    CPC classification number: G06F12/00 G06F8/654

    Abstract: The present invention relates to the field of communications, and in particular, to a method and a system for dynamically upgrading a chip and a baseboard management controller. The method includes: obtaining an upgrade file that is used for upgrading a chip; upgrading, based on the upgrade file, data in a flash memory that is used for storing data of the chip, and not performing a reset operation on the chip at this time; and when it is acquired through detection that the state of a service system that is connected to the chip is a service idle state, replicating the upgraded data in the flash memory to a random access memory in the chip, and performing a reset operation on the chip. According to the present invention, the availability and maintainability of the system are improved.

    Abstract translation: 本发明涉及通信领域,特别涉及用于动态升级芯片和基板管理控制器的方法和系统。 该方法包括:获取用于升级芯片的升级文件; 基于升级文件升级用于存储芯片数据的闪存中的数据,并且此时不对芯片执行复位操作; 并且当通过检测获取连接到芯片的服务系统的状态是服务空闲状态时,将闪速存储器中的升级数据复制到芯片中的随机存取存储器,并对该芯片执行复位操作 芯片。 根据本发明,提高了系统的可用性和可维护性。

    Packet backpressure detection method, apparatus, and device

    公开(公告)号:US10599549B2

    公开(公告)日:2020-03-24

    申请号:US16250168

    申请日:2019-01-17

    Abstract: A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

    DATA PROCESSING METHOD AND APPARATUS AND HETEROGENEOUS SYSTEM

    公开(公告)号:US20230114242A1

    公开(公告)日:2023-04-13

    申请号:US18046151

    申请日:2022-10-12

    Abstract: A data processing method and apparatus, and a heterogeneous system, pertaining to the field of computer technologies are provided. The heterogeneous system includes a processor connected to an accelerator. A secondary memory is connected to the accelerator. The processor is configured to write to-be-processed data into the secondary memory and trigger the accelerator to access and process the to-be-processed data stored in the secondary memory according to a processing instruction. The accelerator is configured to write a processing result of the to-be-processed data into the secondary memory and to trigger the processor to read the processing result. Processing efficiency is enhanced by reducing the number of times of interaction between the processor and the accelerator and simplifying the procedure for data processing.

    Packet backpressure detection method, apparatus, and device

    公开(公告)号:US11550694B2

    公开(公告)日:2023-01-10

    申请号:US16653326

    申请日:2019-10-15

    Abstract: A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

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