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公开(公告)号：US20200295867A1
公开(公告)日：2020-09-17
申请号：US16892731
申请日：2020-06-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yiqun Ge , Xiaocheng Liu
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.
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公开(公告)号：US10700808B2
公开(公告)日：2020-06-30
申请号：US16163169
申请日：2018-10-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yiqun Ge , Xiaocheng Liu , Gongzheng Zhang , Jian Wang , Nan Cheng , Qifan Zhang
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.
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公开(公告)号：US11368249B2
公开(公告)日：2022-06-21
申请号：US17132566
申请日：2020-12-23
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Rong Li , Gongzheng Zhang , Ying Chen , Xiaocheng Liu , Jun Wang
Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
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公开(公告)号：US20200092035A1
公开(公告)日：2020-03-19
申请号：US16693865
申请日：2019-11-25
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yigun Ge , Xiaocheng Liu
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device.
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公开(公告)号：US10209299B2
公开(公告)日：2019-02-19
申请号：US15432741
申请日：2017-02-14
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zhen Xu , Yuqing Zhao , Xiaocheng Liu
IPC: G01R31/28 , G06F11/00 , G01R31/317 , G06F11/25 , G01R31/3185
Abstract: Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.
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Patent Agency Ranking
公开(公告)号：US20170177522A1
公开(公告)日：2017-06-22
申请号：US15453020
申请日：2017-03-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiaocheng Liu , Xianluo Huang , Yuqing Zhao
IPC: G06F13/362 , G06F13/40
CPC classification number: G06F13/3625 , G06F9/3836 , G06F13/4068
Abstract: A processor is disclosed. The processor includes: at least one execution unit group, where each execution unit group in the at least one execution unit group includes multiple serially-connected execution units; and at least one resource unit, where each resource unit in the at least one resource unit is serially connected to one or more execution unit groups in the at least one execution unit group separately. According to the processor, execution units in an execution unit group are serially connected, and a resource unit is serially connected to one or more execution unit groups, so that only a few execution units can be directly connected to the resource unit, and cable layout congestion at the resource unit and resulting signal interference are avoided.
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公开(公告)号：US11444640B2
公开(公告)日：2022-09-13
申请号：US17135061
申请日：2020-12-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiaocheng Liu , Ying Chen , Rong Li
Abstract: The present disclosure relates to encoding method and devices. One example method includes determining N to-be-encoded bits, where the N to-be-encoded bits include information bits and frozen bits, obtaining a first polarization weight vector including polarization weights of N polarized channels, where the N to-be-encoded bits correspond to the N polarized channels, determining positions of the information bits based on the first polarization weight vector, and performing polar encoding on the N to-be-encoded bits to obtain polar-encoded bits.
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公开(公告)号：US11171673B2
公开(公告)日：2021-11-09
申请号：US16923898
申请日：2020-07-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiajie Tong , Huazi Zhang , Yunfei Qiao , Rong Li , Xiaocheng Liu , Jun Wang
Abstract: A decoding method and apparatus are provided, to improve a degree of parallelism in decoded bit decisions and reduce a decoding delay. The method includes: performing a hard decision on each LLR in an inputted LLR vector having a length of M to obtain a first vector, where M≤N and N is a length of to-be-decoded information; sequentially performing negation of some elements of the first vector to obtain L vectors; and then determining decoding results of the LLR vector based on the L vectors.
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公开(公告)号：US10892851B2
公开(公告)日：2021-01-12
申请号：US16295151
申请日：2019-03-07
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Rong Li , Gongzheng Zhang , Ying Chen , Xiaocheng Liu , Jun Wang
Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
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公开(公告)号：US20180076922A1
公开(公告)日：2018-03-15
申请号：US15699967
申请日：2017-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yiqun Ge , Xiaocheng Liu , Gongzheng Zhang , Jian Wang , Nan Cheng , Qifan Zhang
CPC classification number: H04L1/0009 , H03M13/11 , H03M13/13 , H03M13/611 , H03M13/616 , H03M13/6362 , H04L1/0041 , H04L1/0043 , H04L1/0061 , H04L1/0063 , H04L1/0065
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.
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