公开(公告)号：US10700808B2

公开(公告)日：2020-06-30

申请号：US16163169

申请日：2018-10-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huazi Zhang ,  Jiajie Tong ,  Rong Li ,  Jun Wang ,  Wen Tong ,  Yiqun Ge ,  Xiaocheng Liu ,  Gongzheng Zhang ,  Jian Wang ,  Nan Cheng ,  Qifan Zhang

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/13 ,  H03M13/11

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

公开(公告)号：US09928074B2

公开(公告)日：2018-03-27

申请号：US14480035

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38 ,  G06F13/42

CPC classification number: G06F9/3871 ,  G06F9/3836 ,  G06F9/3885 ,  G06F13/4204 ,  G06F13/4282

Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

公开(公告)号：US09495316B2

公开(公告)日：2016-11-15

申请号：US14480330

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。

公开(公告)号：US09740487B2

公开(公告)日：2017-08-22

申请号：US14480522

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: G06F9/30 ,  G06F15/76 ,  G06F1/08 ,  G06F1/10 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

公开(公告)号：US09325520B2

公开(公告)日：2016-04-26

申请号：US14325117

申请日：2014-07-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/48 ,  H04L12/433 ,  G06F15/16

CPC classification number: H04L12/433 ,  G06F9/3871 ,  G06F15/16

Abstract: Embodiments are provided for adding a token jump logic to an asynchronous processor with token passing. The token jump logic allows token forward jumps and token backward jumps over a cascade of token processing logics in the processor. An embodiment method includes determining, using a token jump logic coupled to a cascade of token processing logics, whether to administer a token forward jump or a token backward jump of a token signal passing through the token processing logics. The token forward jump and token backward jump allow the token signal to skip one or more token processing logics in the cascade. The method further includes monitoring, for each of the token processing logics, a polarity status of a token sense logic, and inverting the polarity status according to the determination at the token jump logic.

Abstract translation: 提供了实施例，用令牌传递将令牌跳转逻辑添加到异步处理器。 令牌跳转逻辑允许在处理器中的令牌处理逻辑级联的令牌向前跳跃和令牌向后跳转。 实施例方法包括使用耦合到令牌处理逻辑的级联的令牌跳转逻辑来确定是否管理通过令牌处理逻辑的令牌信号的令牌前向跳转或令牌反向跳转。 令牌向前跳转和令牌反向跳转允许令牌信号跳过级联中的一个或多个令牌处理逻辑。 该方法还包括针对令牌处理逻辑中的每一个监视令牌检测逻辑的极性状态，以及根据令牌跳转逻辑处的确定来反转极性状态。

公开(公告)号：US10318305B2

公开(公告)日：2019-06-11

申请号：US14477536

申请日：2014-09-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/448

Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

公开(公告)号：US10133578B2

公开(公告)日：2018-11-20

申请号：US14480541

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

公开(公告)号：US20180076922A1

公开(公告)日：2018-03-15

申请号：US15699967

申请日：2017-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huazi Zhang ,  Jiajie Tong ,  Rong Li ,  Jun Wang ,  Wen Tong ,  Yiqun Ge ,  Xiaocheng Liu ,  Gongzheng Zhang ,  Jian Wang ,  Nan Cheng ,  Qifan Zhang

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/00

CPC classification number: H04L1/0009 ,  H03M13/11 ,  H03M13/13 ,  H03M13/611 ,  H03M13/616 ,  H03M13/6362 ,  H04L1/0041 ,  H04L1/0043 ,  H04L1/0061 ,  H04L1/0063 ,  H04L1/0065

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.

公开(公告)号：US09606801B2

公开(公告)日：2017-03-28

申请号：US14480531

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Tong ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Tao Huang

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/30 ,  G06F9/38 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

公开(公告)号：US09489200B2

公开(公告)日：2016-11-08

申请号：US14480491

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: G06F5/06 ,  G06F15/177 ,  G06F9/30 ,  G06F9/38 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

Abstract translation: 无时钟异步处理电路或系统被配置为以多种模式操作。 在初始化模式（例如，复位，初始化，启动）中，与异步电路相关联的自定时发生器被配置为在接收到触发之后的第一时间段内产生有效完成信号（锁存输出处理的数据） 信号。 在正常模式下，自定时发生器被配置为在接收到触发信号之后的第二时间段内产生有效完成信号。 在一个实施例中，在初始化模式期间，异步电路比正常模式下的锁存输出慢。