公开(公告)号：US5923868A

公开(公告)日：1999-07-13

申请号：US957003

申请日：1997-10-23

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Newman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Newman

IPC分类号： H04Q3/545 ,  H04Q3/68 ,  H04Q11/04 ,  G06F15/173 ,  G06F17/16

CPC分类号： H04Q11/0407 ,  H04Q11/04 ,  H04Q3/545 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1305 ,  H04Q2213/13141 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  Y10T307/74 ,  Y10T307/76

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US06243664B1

公开(公告)日：2001-06-05

申请号：US09181084

申请日：1998-10-27

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： G06F15173

CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077 ,  Y10T307/74

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列被耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US5689686A

公开(公告)日：1997-11-18

申请号：US822769

申请日：1997-03-21

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： H04Q3/545 ,  H04Q3/68 ,  H04Q11/04 ,  H04Q3/04

CPC分类号： H04Q11/0407 ,  H04Q11/04 ,  H04Q3/545 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1305 ,  H04Q2213/13141 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  Y10T307/74 ,  Y10T307/76

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。

公开(公告)号：US5848066A

公开(公告)日：1998-12-08

申请号：US705990

申请日：1996-08-30

申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

IPC分类号： H03K19/173 ,  H03K19/177 ,  H04Q11/04

CPC分类号： H03K19/17736 ,  H03K19/1737

摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

公开(公告)号：US5917337A

公开(公告)日：1999-06-29

申请号：US578201

申请日：1995-12-29

申请人： W. Alfred Graf

发明人： W. Alfred Graf

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

摘要翻译： 通过使用反熔丝实现多个配置和数据转换选项的可编程I / O单元。 实现了通过使用I / O单元中的寄存器来实现数据转换功能从而节省用于实现其他功能的FPGA逻辑单元的逻辑和寄存器来实现这种设计所必需的逻辑利用率和减少的部件数量。 串行到并行和并行到串行的数据转换操作利用相邻单元中的相邻寄存器执行移位操作。

公开(公告)号：US5786710A

公开(公告)日：1998-07-28

申请号：US581105

申请日：1995-12-29

申请人： W. Alfred Graf

发明人： W. Alfred Graf

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1736

摘要： A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

公开(公告)号：US5869982A

公开(公告)日：1999-02-09

申请号：US580770

申请日：1995-12-29

申请人： W. Alfred Graf

发明人： W. Alfred Graf

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1736

摘要： A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

公开(公告)号：US5760719A

公开(公告)日：1998-06-02

申请号：US580836

申请日：1995-12-29

申请人： W. Alfred Graf

发明人： W. Alfred Graf

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17744 ,  H03K19/1737 ,  H03K19/1778

摘要： A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

公开(公告)号：US5811989A

公开(公告)日：1998-09-22

申请号：US967435

申请日：1997-11-11

申请人： W. Alfred Graf

发明人： W. Alfred Graf

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.