公开(公告)号：US20110305066A1

公开(公告)日：2011-12-15

申请号：US12815369

申请日：2010-06-14

申请人： Hagop NAZARIAN ,  Sung Hyun Jo

发明人： Hagop NAZARIAN ,  Sung Hyun Jo

IPC分类号： G11C11/00 ,  G01R31/28

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/15 ,  G11C2213/33

摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

摘要翻译： 一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

公开(公告)号：US20110305065A1

公开(公告)日：2011-12-15

申请号：US12815318

申请日：2010-06-14

申请人： Hagop NAZARIAN ,  Sung Hyun Jo

发明人： Hagop NAZARIAN ,  Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C14/0045 ,  G11C2213/33 ,  G11C2213/53 ,  H01L29/7881 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148

摘要： A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

摘要翻译： 非易失性可变电容性器件包括限定在衬底上的电容器，所述电容器具有上电极和具有第一电极，第二电极和设置在第一和第二电极之间的开关层的电阻存储单元。 电阻性存储单元被配置为根据所接收的电信号被放置在多个电阻状态。 电容器件的上电极耦合到电阻存储器单元的第二电极。 电阻式存储单元是双端器件。

公开(公告)号：US20120320660A1

公开(公告)日：2012-12-20

申请号：US13592224

申请日：2012-08-22

申请人： Hagop NAZARIAN ,  Sung Hyun Jo

发明人： Hagop NAZARIAN ,  Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/15 ,  G11C2213/33

摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

摘要翻译： 一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

公开(公告)号：US20130194002A1

公开(公告)日：2013-08-01

申请号：US13626374

申请日：2012-09-25

申请人： Hagop NAZARIAN

发明人： Hagop NAZARIAN

IPC分类号： H03K19/0175

CPC分类号： H03K19/017581 ,  G06J1/00

摘要： An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

摘要翻译： 混合模式集成电路系统的模拟部分包括多个模拟输入单元，多个模拟输出单元和互连阵列。 输入单元配置为编程模拟功能。 输出单元被配置为提供与编程的模拟功能相对应的模拟和数字输出。 互连阵列将编程的模拟功能处理成指示模拟功能的信号。 互连阵列选择性地将信号提供给多个模拟输出单元。

公开(公告)号：US20110122708A1

公开(公告)日：2011-05-26

申请号：US12346699

申请日：2008-12-30

申请人： Hagop NAZARIAN ,  Imran KHAN ,  Chieu-Yin CHIA

发明人： Hagop NAZARIAN ,  Imran KHAN ,  Chieu-Yin CHIA

IPC分类号： G11C16/06

CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/3454

摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.

摘要翻译： 提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。 半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。 控制器向位线解码器提供存储器操作信号，并且在对多个预定存储器阵列的位线进行预充电之后，根据存储器操作对多个预定存储器阵列中的一个或多个中的选定存储单元执行存储器操作 信号。 位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。 位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行 阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。