公开(公告)号：US20190108881A1

公开(公告)日：2019-04-11

申请号：US16158852

申请日：2018-10-12

申请人： Micron Technology, Inc.

发明人： Alessio Spessot ,  Paolo Fantini ,  Massimo Ferro

IPC分类号： G11C13/00

CPC分类号： G11C13/0064 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092

摘要： Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

公开(公告)号：US20180358552A1

公开(公告)日：2018-12-13

申请号：US15616320

申请日：2017-06-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin W. Brew ,  Talia S. Gershon ,  Seyoung Kim ,  Dennis M. Newns ,  Teodor K. Todorov

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/1206 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/53 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608

摘要： A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.

公开(公告)号：US20180108409A1

公开(公告)日：2018-04-19

申请号：US15714562

申请日：2017-09-25

申请人： Microsemi SoC Corp.

发明人： Volker Hecht

IPC分类号： G11C13/00

CPC分类号： G11C13/0059 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/79

摘要： A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.

公开(公告)号：US09934838B1

公开(公告)日：2018-04-03

申请号：US15591834

申请日：2017-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  G11C13/00 ,  G06N3/04 ,  G06N3/08

CPC分类号： G11C11/2273 ,  G06N3/04 ,  G06N3/084 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/54 ,  G11C11/56 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/53

摘要： A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.

公开(公告)号：US09887007B1

公开(公告)日：2018-02-06

申请号：US15381703

申请日：2016-12-16

申请人： Industrial Technology Research Institute

发明人： Chia-Chen Kuo ,  Shyh-Shyuan Sheu

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/003 ,  G11C13/0061 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2213/79

摘要： A variable-resistance memory and a writing method thereof are provided. The variable-resistance memory includes a variable-resistance memory cell, a voltage-signal-generation circuit, a switch circuit, a detection circuit, and a controller. The variable-resistance memory cell includes a variable-resistance component and a transistor. The voltage-signal-generation circuit is coupled to the control terminal of the transistor. The switch circuit is coupled to the variable-resistance component and transistor. The detection circuit is coupled to a voltage source and the switch circuit. The controller is coupled to the voltage-signal-generation circuit, switch circuit, and detection circuit. When the controller performs a writing operation on the variable-resistance memory cell, the voltage-signal-generation circuit provides a voltage signal to the transistor, and the detection circuit continuously detects whether the variable-resistance component performs a resistance conversion. If the resistance conversion occurs, then the controller stops the writing operation.

公开(公告)号：US20180018134A1

公开(公告)日：2018-01-18

申请号：US15467374

申请日：2017-03-23

申请人： SK hynix Inc.

发明人： Jae-Yong Kang

IPC分类号： G06F3/06 ,  G11C13/00

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

摘要： Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.

公开(公告)号：US20170365338A1

公开(公告)日：2017-12-21

申请号：US15128020

申请日：2015-03-24

申请人： TOHOKU UNIVERSITY

发明人： Takahiro Hanyu ,  Daisuke Suzuki ,  Masanori Natsui ,  Akira Mochizuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC分类号： G11C13/00 ,  G11C11/16

CPC分类号： G11C13/0064 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0083

摘要： A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.

公开(公告)号：US09805794B1

公开(公告)日：2017-10-31

申请号：US14716386

申请日：2015-05-19

申请人： Crossbar, Inc.

发明人： Zhi Li ,  Tanmay Kumar ,  Sung Hyun Jo

IPC分类号： G11C13/00 ,  G11C11/56

CPC分类号： G11C13/0097 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092

摘要： Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.

公开(公告)号：US09805770B1

公开(公告)日：2017-10-31

申请号：US15217739

申请日：2016-07-22

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Emmanuelle J. Merced Grafals ,  John Paul Strachan ,  Noraica Davila

IPC分类号： G11C7/00 ,  G11C13/00 ,  G11C11/56 ,  H01L23/528

CPC分类号： G11C7/00 ,  G11C11/5614 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2213/79 ,  H01L23/528

摘要： A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

公开(公告)号：US20170256314A1

公开(公告)日：2017-09-07

申请号：US15511708

申请日：2015-06-12

申请人： Fudan University

发明人： Yinyin LIN ,  Jianguo YANG

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092

摘要： The present invention relates to resistive random access memory (ReRAM). Disclosed are a ReRAM and write operation method thereof. The write operation method comprises monitoring, under a pre-operation signal bias, whether a conversion from a high resistance stage (HRS)/low resistance stage (LRS) to a LRS/HRS begins to occur, and controlling a change in a conversion operation signal, thus conducting a setting/resetting operation. The write operation method improves the storage performance of the ReRAM.