公开(公告)号：US20070133289A1

公开(公告)日：2007-06-14

申请号：US11606535

申请日：2006-11-30

申请人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

发明人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

摘要： The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and −20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.

摘要翻译： 本发明的器件包括形成在半导体衬底的预定区域并彼此平行延伸的多个隔离层。 本发明的器件还包括放置在深N阱和NMOS顶部的高电压PMOS，其放置在外围区域的深N阱内的三重P阱上方，以通过周围的正和负高电压 + 20V和-20V到细胞区域。 在一个实施例中，单元阵列，源极线和位线都被放置在P衬底的顶部上，而没有深N阱或三重P阱。 在其他实施例中，将单元阵列，源极线和位线放置在深N阱和三重P阱的顶部。