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    NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same
    1.
    发明申请
    NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same 审中-公开
    具有高压PMOS和嵌入式多晶硅的NAND型闪存器件及其制造方法

    公开(公告)号：US20070133289A1

    公开(公告)日：2007-06-14

    申请号：US11606535

    申请日：2006-11-30

    申请人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

    发明人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

    摘要： The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and −20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.

    摘要翻译： 本发明的器件包括形成在半导体衬底的预定区域并彼此平行延伸的多个隔离层。 本发明的器件还包括放置在深N阱和NMOS顶部的高电压PMOS，其放置在外围区域的深N阱内的三重P阱上方，以通过周围的正和负高电压 + 20V和-20V到细胞区域。 在一个实施例中，单元阵列，源极线和位线都被放置在P衬底的顶部上，而没有深N阱或三重P阱。 在其他实施例中，将单元阵列，源极线和位线放置在深N阱和三重P阱的顶部。

    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
    2.
    发明申请
    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
    组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作

    公开(公告)号：US20070133341A1

    公开(公告)日：2007-06-14

    申请号：US11633334

    申请日：2006-12-04

    申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C7/10

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

    摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

    摘要翻译： 描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。 使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。 闪存单元被块擦除时，EEPROM单元被字节擦除。 小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    3.
    发明申请
    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
    新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US20070047302A1

    公开(公告)日：2007-03-01

    申请号：US11391507

    申请日：2006-03-28

    申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    10.
    发明申请
    Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
    新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US20060171203A1

    公开(公告)日：2006-08-03

    申请号：US11376076

    申请日：2006-03-15

    申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。