公开(公告)号：US20120231593A1

公开(公告)日：2012-09-13

申请号：US13112767

申请日：2011-05-20

申请人： Han-Soo JOO ,  Sang-Hyun OH ,  Yu-Jin PARK

发明人： Han-Soo JOO ,  Sang-Hyun OH ,  Yu-Jin PARK

IPC分类号： H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/1203

摘要： A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

摘要翻译： 一种用于制造3D非易失性存储器件的方法，包括在衬底上形成子沟道，在衬底上形成堆叠层，所述堆叠层包括交替层叠有导电层的多个层间电介质层，选择性地蚀刻堆叠 以形成暴露子通道的第一开放区域，形成主通道导电层以间隙填充第一开放区域，选择性地蚀刻堆叠层和主沟道导电层以形成限定多个的第二开口区域 的主通道，并且形成隔离层以间隙填充第二开口区域。

公开(公告)号：US20130168745A1

公开(公告)日：2013-07-04

申请号：US13605046

申请日：2012-09-06

申请人： Han-Soo JOO

发明人： Han-Soo JOO

IPC分类号： H01L21/20 ,  H01L29/78

CPC分类号： H01L27/11582

摘要： A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole.

摘要翻译： 非易失性存储器件包括栅极结构，其中多个层间电介质层和多个栅电极交替堆叠; 栅极电极位于栅极结构下方; 限定在通过栅电极中的子通道孔; 一对主通道孔，其通过栅极结构限定并与子通道孔连通; 形成在所述一对主通道孔和所述副通道孔的内壁上的通道层; 以及与子通道孔中的沟道层接触的金属物质层。

公开(公告)号：US20110062510A1

公开(公告)日：2011-03-17

申请号：US12881635

申请日：2010-09-14

申请人： Han-Soo JOO

发明人： Han-Soo JOO

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.

摘要翻译： 一种具有串行耦合的多个存储单元的串的非易失性存储器件，其中所述存储单元串包括多个柱状的第二通道，第一通道将所述多个第二通道的下端部分 通道，以及围绕多个第二通道的多个控制栅电极。

公开(公告)号：US20120299087A1

公开(公告)日：2012-11-29

申请号：US13334017

申请日：2011-12-21

申请人： Han-Soo JOO ,  Yu-Jin PARK

发明人： Han-Soo JOO ,  Yu-Jin PARK

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.

摘要翻译： 非易失性存储器件包括栅极结构，其包括在衬底上交替层叠有控制栅极层的第一绝缘层，其中栅极结构沿第一方向延伸，沟道线分别在不同于第二方向的第二方向上延伸到栅极结构上 第一方向，形成在栅极结构和沟道线之间的存储层，并被布置成通过将栅极结构与沟道线电绝缘来捕获电荷，位线触点形成行，其各自沿第一方向延伸并接触第一方向的顶表面 通道线，源极线，其各自在第一方向上延伸并接触通道线的顶表面，其中源极线与位线接触行交替，并且位线位于位线上并且在第 第二个方向。

公开(公告)号：US20130128660A1

公开(公告)日：2013-05-23

申请号：US13475204

申请日：2012-05-18

申请人： Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

发明人： Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

IPC分类号： G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

摘要翻译： 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。