公开(公告)号：US08711630B2

公开(公告)日：2014-04-29

申请号：US13334423

申请日：2011-12-22

申请人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

发明人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  H01L27/11556

摘要： A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.

摘要翻译： 一种非易失性存储器件的编程方法，包括具有多个浮动栅极和多个控制栅极交替布置的存储器单元串，其中每个存储器单元包括一个浮置栅极和两个控制栅极， 浮动门和两个相邻的存储单元共享一个控制门。 编程方法包括将第一编程电压施加到所选择的存储单元的第一控制栅极，以及将高于第一编程电压的第二编程电压施加到所选存储单元的第二控制栅极，并将第一通过电压施加到 与第一控制栅极相邻设置的第三控制栅极和与第二控制栅极相邻设置的第四控制栅极低于第一通过电压的第二通过电压。

公开(公告)号：US08637913B2

公开(公告)日：2014-01-28

申请号：US13304551

申请日：2011-11-25

申请人： Hyun-Seung Yoo ,  Eun-Seok Choi

发明人： Hyun-Seung Yoo ,  Eun-Seok Choi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸并包括掺杂有第一杂质的第一区和设置在第一区下的第二区的通道，多个存储单元和选择晶体管沿着衬底 通道和插入在第一区域和第二区域之间的扩散阻挡层，其中第一杂质的密度高于第二区域的杂质密度。

公开(公告)号：US20130234234A1

公开(公告)日：2013-09-12

申请号：US13607050

申请日：2012-09-07

申请人： Hyun-Seung YOO

发明人： Hyun-Seung YOO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.

摘要翻译： 一种用于制造非易失性存储器件的方法包括形成层叠结构，其中多个层间电介质层和多个第二牺牲层交替堆叠在衬底上，形成沟道层，该沟道层与 通过穿过层叠结构形成穿过第二牺牲层的狭缝，通过选择性地蚀刻层叠结构，去除通过狭缝暴露的第二牺牲层，在通过暴露的通道层上形成外延层，作为由 去除第二牺牲层，以及形成填充去除第二牺牲层的空间的栅电极层，以及插入在栅电极层和外延层之间的存储层。

公开(公告)号：US20120168849A1

公开(公告)日：2012-07-05

申请号：US13304901

申请日：2011-11-28

申请人： Eun-Seok CHOI ,  Hyun-Seung Yoo

发明人： Eun-Seok CHOI ,  Hyun-Seung Yoo

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L28/20

摘要： A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.

摘要翻译： 非易失性存储器件包括：衬底，其具有电阻低于源极线的电阻层，沟道结构包括多个层间电介质层，所述多个层间电介质层与衬底上的多个沟道层交替地淀积;以及 源极线被配置为接触沟道层的侧壁，其中源极线的下端接触电阻层。

公开(公告)号：US07616496B2

公开(公告)日：2009-11-10

申请号：US11771632

申请日：2007-06-29

申请人： Eun Seok Choi ,  Se Jun Kim ,  Kyoung Hwan Park ,  Hyun Seung Yoo

发明人： Eun Seok Choi ,  Se Jun Kim ,  Kyoung Hwan Park ,  Hyun Seung Yoo

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0466

摘要： A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.

摘要翻译： 一种对电荷陷阱型非易失性存储器件进行编程的方法包括将程序脉冲施加到所选择的存储单元，向所选择的存储单元施加去除脉冲，以及将程序验证脉冲施加到存储单元。 电荷陷阱型非易失性存储器件包括具有电荷陷阱存储单元的存储单元阵列，以及用于向电荷陷阱存储单元提供去除脉冲的高电压发生器。

公开(公告)号：US08941172B2

公开(公告)日：2015-01-27

申请号：US13541873

申请日：2012-07-05

申请人： Hyun Seung Yoo

发明人： Hyun Seung Yoo

IPC分类号： H01L29/72 ,  H01L27/115 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L21/76237 ,  G11C16/0466 ,  H01L21/76294 ,  H01L27/11582 ,  H01L29/7926

摘要： A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

公开(公告)号：US08912053B2

公开(公告)日：2014-12-16

申请号：US13607050

申请日：2012-09-07

申请人： Hyun-Seung Yoo

发明人： Hyun-Seung Yoo

IPC分类号： H01L21/332 ,  H01L21/00 ,  H01L21/84 ,  H01L21/337 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.

摘要翻译： 一种用于制造非易失性存储器件的方法包括形成层叠结构，其中多个层间电介质层和多个第二牺牲层交替堆叠在衬底上，形成沟道层，该沟道层与 通过穿过层叠结构形成穿过第二牺牲层的狭缝，通过选择性地蚀刻层叠结构，去除通过狭缝暴露的第二牺牲层，在通过暴露的通道层上形成外延层，作为由 去除第二牺牲层，以及形成填充去除第二牺牲层的空间的栅电极层，以及插入在栅电极层和外延层之间的存储层。

公开(公告)号：US09111797B2

公开(公告)日：2015-08-18

申请号：US13613839

申请日：2012-09-13

申请人： Eun Seok Choi ,  Hyun Seung Yoo

发明人： Eun Seok Choi ,  Hyun Seung Yoo

IPC分类号： H01L29/78 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

摘要： A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

摘要翻译： 三维（3-D）非易失性存储器件包括从衬底的表面突出并被配置为具有倾斜侧壁的支撑件; 每个通道结构被配置为包括层间绝缘层和沟道层，所述层间绝缘层和沟道层交替堆叠在包括支撑件的基板上，沿着支撑件的倾斜侧壁弯曲，其中每个沟道结构包括单元区域和接触区域，并且沟道 层在接触区域中暴露; 选择在通道结构上形成的线; 以及在接触区域处耦合到相应通道层并穿透选择线的柱状通道。

公开(公告)号：US09053977B2

公开(公告)日：2015-06-09

申请号：US13610781

申请日：2012-09-11

申请人： Eun-Seok Choi ,  Hyun-Seung Yoo

发明人： Eun-Seok Choi ,  Hyun-Seung Yoo

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11573 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

摘要翻译： 根据本发明的一个实施例的非易失性存储器件包括：包括P型杂质掺杂区的衬底，包括多个层间绝缘层的沟道结构，所述多个层间绝缘层交替层叠有多个沟道层 基板，与所述多个沟道层的侧壁接触的P型半导体图案，其中所述P型半导体图案的下端接触所述P型杂质掺杂区域，以及设置在所述P型掺杂区域的两侧的源极线 P型半导体图案并与多个沟道层的侧壁接触。

公开(公告)号：US20130113033A1

公开(公告)日：2013-05-09

申请号：US13610781

申请日：2012-09-11

申请人： Eun-Seok CHOI ,  Hyun-Seung Yoo

发明人： Eun-Seok CHOI ,  Hyun-Seung Yoo

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11573 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.