公开(公告)号：US08252654B2

公开(公告)日：2012-08-28

申请号：US12942312

申请日：2010-11-09

申请人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

摘要： In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.

摘要翻译： 在存储单元的制造方法中，设置有基板。 在基板的表面附近形成具有第一导电类型的掺杂区域。 去除衬底的一部分以在衬底中限定多个鳍结构。 在翅片结构之间形成多个隔离结构。 隔离结构的表面低于翅片结构的表面。 栅极结构形成在衬底上并跨越翅片结构。 栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。 源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。

公开(公告)号：US20080087942A1

公开(公告)日：2008-04-17

申请号：US11785322

申请日：2007-04-17

申请人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  G11C11/34 ,  H01L21/336

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785 ,  H01L29/792

摘要： A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

摘要翻译： 提供了包括基板，通道，多层结构，栅极，第一端子和第二端子的垂直沟道存储器。 通道从基板突出并具有顶表面和两个垂直表面。 多层结构设置在通道的两个垂直表面上。 栅极跨层多层结构位于通道的两个垂直表面上方。 第一端子和第二端子分别位于与栅极相对的通道的两侧。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： G11C11/34 ,  H01L21/36

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US20110303968A1

公开(公告)日：2011-12-15

申请号：US12813906

申请日：2010-06-11

申请人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

发明人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

摘要： An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.

摘要翻译： 非易失性存储单元阵列的集成电路在衬底上具有介电堆叠层，并且在介电堆叠层下方的衬底中的注入区域。 电介质堆叠层在平面区域上是连续的，其包括存储非易失性数据的电介质堆叠层的位置，使得这些位置被字线/位线访问。

公开(公告)号：US07701769B2

公开(公告)日：2010-04-20

申请号：US12188499

申请日：2008-08-08

申请人： Hang-Ting Lue ,  Tzu Hsuan Hsu

发明人： Hang-Ting Lue ,  Tzu Hsuan Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

摘要翻译： 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

公开(公告)号：US08481388B2

公开(公告)日：2013-07-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US08072813B2

公开(公告)日：2011-12-06

申请号：US12715996

申请日：2010-03-02

申请人： Hang-Ting Lue ,  Tzu Hsuan Hsu

发明人： Hang-Ting Lue ,  Tzu Hsuan Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

摘要翻译： 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

公开(公告)号：US20100157686A1

公开(公告)日：2010-06-24

申请号：US12715996

申请日：2010-03-02

申请人： Hang-Ting Lue ,  Tzu Hsuan Hsu

发明人： Hang-Ting Lue ,  Tzu Hsuan Hsu

IPC分类号： G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

摘要翻译： 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

公开(公告)号：US20090046506A1

公开(公告)日：2009-02-19

申请号：US12188499

申请日：2008-08-08

申请人： Hang-Ting Lue ,  Tzu Hsuan Hsu

发明人： Hang-Ting Lue ,  Tzu Hsuan Hsu

IPC分类号： G11C16/12

CPC分类号： G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

摘要翻译： 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

公开(公告)号：US20080290391A1

公开(公告)日：2008-11-27

申请号：US11958134

申请日：2007-12-17

申请人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L21/8247 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

摘要： The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.

摘要翻译： 本发明提供了一种存储单元。 存储单元设置在基板上并且包括在基板中限定至少鳍结构的多个隔离结构。 此外，翅片结构的表面高于隔离结构的表面。 存储单元包括掺杂区域，栅极，电荷俘获结构和源极/漏极区域。 掺杂区域位于鳍结构的顶部并且在鳍结构的顶部的表面附近，并且掺杂区域具有第一导电类型。 栅极设置在基板上并跨越翅片结构。 电荷捕获结构设置在栅极和鳍结构之间。 具有第二导电类型的源极/漏极区域设置在由栅极暴露的鳍状结构中，并且第一导电类型不同于第二导电类型。