公开(公告)号：US07209390B2

公开(公告)日：2007-04-24

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C16/00

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。 通过这些再填充循环可以大大提高电荷保持性。

公开(公告)号：US20050237816A1

公开(公告)日：2005-10-27

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/36 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

公开(公告)号：US20100311217A1

公开(公告)日：2010-12-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07763927B2

公开(公告)日：2010-07-27

申请号：US11300813

申请日：2005-12-15

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US08481388B2

公开(公告)日：2013-07-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US20070138539A1

公开(公告)日：2007-06-21

申请号：US11300813

申请日：2005-12-15

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  H01L21/8238

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07590005B2

公开(公告)日：2009-09-15

申请号：US11625236

申请日：2007-01-19

申请人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. The programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷捕获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧穿方法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 电荷捕获存储器的编程是使用衬底瞬态热电子注入进行的，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US08072810B2

公开(公告)日：2011-12-06

申请号：US12985743

申请日：2011-01-06

申请人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

发明人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07881112B2

公开(公告)日：2011-02-01

申请号：US12538582

申请日：2009-08-10

申请人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

发明人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

公开(公告)号：US20090296474A1

公开(公告)日：2009-12-03

申请号：US12538582

申请日：2009-08-10

申请人： TZU HSUAN HSU ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： TZU HSUAN HSU ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。