公开(公告)号：US20050003308A1

公开(公告)日：2005-01-06

申请号：US10811509

申请日：2004-03-29

申请人： Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

发明人： Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  G03F7/00

CPC分类号： H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

摘要： In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.

摘要翻译： 为了在具有选择晶体管的存储单元的布置的存储器模块中制造接触孔平面，在半导体衬底上具有半导体表面上相互邻近的栅极电极轨迹的布置，在半导体上形成绝缘体层 表面和牺牲层随后形成在绝缘体层上，然后在牺牲层上产生材料插塞以便限定相互相邻的栅极电极轨道之间的接触开口，牺牲层被蚀刻以形成具有下面牺牲的材料塞 在玻璃质层的生产之后，在相邻的栅电极轨道之间的接触开口上方露出牺牲层块，形成基本平坦的表面，然后从玻璃质层蚀刻牺牲层材料，并且 未覆盖的绝缘体材料在触点上方移除 并且最后，用导电材料填充接触开口区域。

公开(公告)号：US07018781B2

公开(公告)日：2006-03-28

申请号：US10811509

申请日：2004-03-29

申请人： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

发明人： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC分类号： G03F7/00

CPC分类号： H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

摘要翻译： 公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。 可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。