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1.发明申请Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement 审中-公开使用In-SITU多重等离子体处理晶体管改进的层压应力覆盖层公开(公告)号：US20090152639A1
公开(公告)日：2009-06-18
申请号：US11959111
申请日：2007-12-18
申请人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L29/94 , H01L21/31 , H01L21/8238 , H01L23/58
CPC分类号： H01L21/022 , C23C14/0652 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/3105 , H01L21/3185 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译： 集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。 该增加受到PMD衬套的厚度的限制。 本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。 将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。 本发明的PMD衬垫由3〜10层构成。 可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。 还要求一种包含本发明的PMD衬垫的IC及其形成方法。
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2.发明申请Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement 有权使用In-SITU多重等离子体处理晶体管改进的层压应力覆盖层公开(公告)号：US20110027953A1
公开(公告)日：2011-02-03
申请号：US12904593
申请日：2010-10-14
申请人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L21/8238
CPC分类号： H01L21/3185 , C23C14/0652 , C23C16/56 , H01L21/3105 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译： 集成电路（IC）通常包含具有压缩应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。 该增加受到PMD衬套的厚度的限制。 本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。 将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。 本发明的PMD衬垫由3〜10层构成。 可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。 还要求一种包含本发明的PMD衬垫的IC及其形成方法。
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3.发明授权Controlled oxide growth over polysilicon gates for improved transistor characteristics 有权在多晶硅栅极上控制氧化物生长，以改善晶体管特性公开(公告)号：US06352900B1
公开(公告)日：2002-03-05
申请号：US09618404
申请日：2000-07-18
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28247
摘要： A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).
摘要翻译： 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。
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公开(公告)号：US06563175B2
公开(公告)日：2003-05-13
申请号：US09961615
申请日：2001-09-24
IPC分类号： H01L2362
CPC分类号： H01L27/027 , H01L29/66507 , Y10S977/70
摘要： An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.
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5.发明授权NMOS ESD protection device with thin silicide and methods for making same 有权具有薄硅化物的NMOS ESD保护器件及其制造方法公开(公告)号：US06835623B2
公开(公告)日：2004-12-28
申请号：US10374333
申请日：2003-02-24
IPC分类号： H01L218232
CPC分类号： H01L27/027 , H01L29/66507 , Y10S977/70
摘要： An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.
摘要翻译： 公开了一种NMOS ESD钳位装置及其制造方法，其中器件包括形成在半导体衬底中的N型漏极和源极区域以及覆盖在源极和漏极区域之间的衬底中的P型沟道区域的栅极。 在第一厚度的漏极和/或源极区域中形成第一硅化物区域。 第二薄硅化物区形成在栅极和漏极之间的衬底中，具有小于第一厚度的第二厚度，其中，薄硅化物增加器件的ESD电流钳位能力，以提供改进的ESD电路保护。
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