公开(公告)号：US07358765B2

公开(公告)日：2008-04-15

申请号：US11066336

申请日：2005-02-23

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US07836113B2

公开(公告)日：2010-11-16

申请号：US11539799

申请日：2006-10-09

申请人： Ravi Sunkavalli ,  Hare K. Verma ,  Manoj Gunwani ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare K. Verma ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： G06F7/38

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. It a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US07439768B2

公开(公告)日：2008-10-21

申请号：US11539777

申请日：2006-10-09

申请人： Ravi Sunkavalli ,  Hare K. Verma ,  Manoj Gunwani ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare K. Verma ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In some embodiments, the configurable logic function comprises a plurality of look-up tables coupled to a multiplexer with configurable bits that is capable to perform a four 4-input look-up table, one 6-input look-up tables or a 4-to-1 multiplexer. In the first function that operates as the four 4-input look-up table, the dedicated logic cell has four look-up tables for receiving four inputs respectively. In the second function that operates as one 6-input look-up table, a fifth input from a multiplexer and a sixth input from a multiplexer are added to the four inputs. In the third function that operates as a 4-to-1 multiplexer, a multiplexer receives four inputs respectively from the four look-up tables with two select lines.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在一些实施例中，可配置逻辑功能包括耦合到多路复用器的多个查找表，其具有能够执行四个4输入查询表，一个6输入查找表或4- 一对多路复用器。 在作为四个4输入查找表运行的第一个功能中，专用逻辑单元有四个查找表，用于分别接收四个输入。 在作为一个6输入查找表操作的第二功能中，来自多路复用器的第五输入和来自多路复用器的第六输入被添加到四个输入。 在作为4对1多路复用器工作的第三个功能中，多路复用器通过两条选择线分别从四个查找表中接收四个输入。

公开(公告)号：US07414431B2

公开(公告)日：2008-08-19

申请号：US11539790

申请日：2006-10-09

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

公开(公告)号：US08429214B2

公开(公告)日：2013-04-23

申请号：US12885103

申请日：2010-09-17

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US20110010406A1

公开(公告)日：2011-01-13

申请号：US12885103

申请日：2010-09-17

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US07414432B2

公开(公告)日：2008-08-19

申请号：US11539825

申请日：2006-10-09

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic function, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and a sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US07814136B1

公开(公告)日：2010-10-12

申请号：US11344694

申请日：2006-02-01

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US07417456B2

公开(公告)日：2008-08-26

申请号：US11539809

申请日：2006-10-09

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

公开(公告)号：US07368941B2

公开(公告)日：2008-05-06

申请号：US11065019

申请日：2005-02-23

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

IPC分类号： H03K19/173

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。