公开(公告)号：US07724760B2

公开(公告)日：2010-05-25

申请号：US10639269

申请日：2003-08-12

申请人： Hari Balakrishnan ,  Srinivas Devadas ,  Arvind Mithal

发明人： Hari Balakrishnan ,  Srinivas Devadas ,  Arvind Mithal

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L47/24 ,  H04L47/39 ,  H04L47/50 ,  H04L47/52 ,  H04L47/6215 ,  H04L47/6255 ,  H04L49/101 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3045

摘要： A method for selecting a queue for service across a shared link. The method includes classifying each queue from a group of queues within a plurality of ingresses into one tier of a number “N” of tiers. The number “N” is greater than or equal to 2. Information about allocated bandwidth is used to classify at least some of the queues into the tiers. Each tier is assigned a different priority. The method also includes matching queues to available egresses by matching queues classified within tiers with higher priorities before matching queues classified within tiers with lower priorities.

摘要翻译： 一种用于通过共享链路选择服务队列的方法。 该方法包括将来自多个入口内的一组队列中的每个队列分成层数“N”的一层。 数字“N”大于或等于2.关于分配的带宽的信息用于将至少一些队列分类到层级中。 每个层都有不同的优先级。 该方法还包括通过匹配在具有较低优先级的层级中分类的队列之前匹配在具有较高优先级的层级中分类的队列来匹配队列到可用出口。

公开(公告)号：US08108810B2

公开(公告)日：2012-01-31

申请号：US12390853

申请日：2009-02-23

申请人： James C Hoe ,  Arvind Mithal

发明人： James C Hoe ,  Arvind Mithal

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of a synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

摘要翻译： 一种用于通过首先接受根据一组状态转换规则来更新存储值的异步系统的指定来指定和合成同步数字电路的方法。 例如，状态转换规则被指定为术语重写系统（TRS），其中每个规则指定允许的状态转换的数量，并且包括对存储的值的逻辑前提条件和在状态转换之后存储的值的功能规范 在状态转换之前的存储值。 异步电路的规范被转换为同步电路的规格，其中可以在每个时钟周期期间发生多个状态转换。 该方法包括识别状态转换集合，例如通过识别TRS规则集合，其可以在单个时钟周期期间发生，并且形成同步电路的规范，以允许单个集合中的任何状态转换在任何特定的时间段期间发生 时钟周期。

公开(公告)号：US20090268628A1

公开(公告)日：2009-10-29

申请号：US12390853

申请日：2009-02-23

申请人： James C. Hoe ,  Arvind Mithal

发明人： James C. Hoe ,  Arvind Mithal

IPC分类号： H04L12/26

CPC分类号： G06F17/5045

摘要： A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of a synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

摘要翻译： 一种用于通过首先接受根据一组状态转换规则来更新存储值的异步系统的指定来指定和合成同步数字电路的方法。 例如，状态转换规则被指定为术语重写系统（TRS），其中每个规则指定允许的状态转换的数量，并且包括对存储的值的逻辑前提条件和在状态转换之后存储的值的功能规范 在状态转换之前的存储值。 异步电路的规范被转换为同步电路的规格，其中可以在每个时钟周期期间发生多个状态转换。 该方法包括识别状态转换集合，例如通过识别TRS规则集合，其可以在单个时钟周期期间发生，并且形成同步电路的规范，以允许单个集合中的任何状态转换在任何特定的时间段期间发生 时钟周期。

公开(公告)号：US20100117683A1

公开(公告)日：2010-05-13

申请号：US12614771

申请日：2009-11-09

申请人： Michal Karczmarek ,  Arvind Mithal ,  Muralidaran Vijayaraghavan

发明人： Michal Karczmarek ,  Arvind Mithal ,  Muralidaran Vijayaraghavan

IPC分类号： H03K19/00 ,  G06N5/02 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5059 ,  G06F2217/84

摘要： Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time).

摘要翻译： 在同步数字系统中启用单周期调度以及调度多周期规则，其行为由异步系统规范（例如，TRS）来管理提供了一种在异步系统的状态转换时允许复杂动作的方法，而不需要 复杂的动作在逻辑中合成，必须在单个时钟周期内执行。 例如，相对不频繁的动作可以包括确定系统的最大时钟频率的关键定时路径。 通过允许这种不频繁的动作需要多个时钟周期，即使该动作需要更多的绝对时间，其他动作也可能需要较少的绝对时间，因为能够以更高的时钟速率操作同步系统。 然后，整个系统可以更快地进行操作（例如，按照每单位绝对时间的平均规则数量测量）。

公开(公告)号：US07392352B2

公开(公告)日：2008-06-24

申请号：US11176518

申请日：2005-07-07

申请人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

发明人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

IPC分类号： G06F12/00

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0817 ,  G06F12/0826 ,  G06F12/084

摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

摘要翻译： 包括分层存储器系统和一个或多个处理器的计算机体系结构。 处理器执行存储器访问指令，其语义是根据存储器系统的层次结构定义的。 也就是说，不是试图保持所有处理器共享存储器系统的错觉，使得一个处理器所做的改变对于其他处理器是立即可见的，所以存储器访问指令明确地解决对处理器特定存储器的访问以及数据传输 在处理器特定的存储器和共享存储器系统之间。 存储器系统的各种替代实施例与这些指令兼容。 这些替代实施例不改变使用存储器访问指令的计算机程序的语义含义，而是允许不同的方法来实现数据从一个处理器到另一处理器的实际传递。

公开(公告)号：US20060004967A1

公开(公告)日：2006-01-05

申请号：US11176518

申请日：2005-07-07

申请人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

发明人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

IPC分类号： G06F12/00

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0817 ,  G06F12/0826 ,  G06F12/084

摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

公开(公告)号：US20050254436A1

公开(公告)日：2005-11-17

申请号：US11142003

申请日：2005-05-31

申请人： James Hoe ,  Arvind Mithal

发明人： James Hoe ,  Arvind Mithal

IPC分类号： G06F17/50 ,  H04L1/00

CPC分类号： G06F17/5045

摘要： A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of a synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

公开(公告)号：US06597664B1

公开(公告)日：2003-07-22

申请号：US09377372

申请日：1999-08-19

申请人： Arvind Mithal ,  James C. Hoe

发明人： Arvind Mithal ,  James C. Hoe

IPC分类号： H04L1266

CPC分类号： G06F17/5045

摘要： A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of an synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

摘要翻译： 一种用于通过首先接受根据一组状态转换规则来更新存储值的异步系统的指定来指定和合成同步数字电路的方法。 例如，状态转换规则被指定为术语重写系统（TRS），其中每个规则指定允许的状态转换的数量，并且包括对存储的值的逻辑前提条件和在状态转换之后存储的值的功能规范 在状态转换之前的存储值。 异步电路的规范被转换为同步电路的规格，其中可以在每个时钟周期期间发生多个状态转换。 该方法包括识别状态转换集合，例如通过识别TRS规则集合，其可以在单个时钟周期期间发生，并且形成同步电路的规范，以允许单个集合中的任何状态转换在任何特定的时间段期间发生 时钟周期。

公开(公告)号：US08350594B2

公开(公告)日：2013-01-08

申请号：US12614771

申请日：2009-11-09

申请人： Michal Karczmarek ,  Arvind Mithal ,  Muralidaran Vijayaraghavan

发明人： Michal Karczmarek ,  Arvind Mithal ,  Muralidaran Vijayaraghavan

IPC分类号： H04J3/16

CPC分类号： G06F17/505 ,  G06F17/5059 ,  G06F2217/84

摘要： Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time).

摘要翻译： 在同步数字系统中启用单周期调度以及调度多周期规则，其行为由异步系统规范（例如，TRS）来管理提供了一种在异步系统的状态转换时允许复杂动作的方法，而不需要 复杂的动作在逻辑中合成，必须在单个时钟周期内执行。 例如，相对不频繁的动作可以包括确定系统的最大时钟频率的关键定时路径。 通过允许这种不频繁的动作需要多个时钟周期，即使该动作需要更多的绝对时间，其他动作也可能需要较少的绝对时间，因为能够以更高的时钟速率操作同步系统。 然后，整个系统可以更快地进行操作（例如，按照每单位绝对时间的平均规则数量测量）。

公开(公告)号：US07716608B2

公开(公告)日：2010-05-11

申请号：US11421612

申请日：2006-06-01

申请人： Arvind Mithal ,  Daniel L. Rosenband

发明人： Arvind Mithal ,  Daniel L. Rosenband

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A scheduling approach enables scheduling sequential execution of rules in a single cycle of a synchronous system without necessarily requiring explicit implementation of a composite rule for each sequence of rules than may be composed. One method for designing a synchronous digital system includes using modules with multiple successive interfaces such that within the a single clocked cycle, each module performs a function equivalent to completing interactions through one of its interfaces before performing interactions through any succeeding one of its interfaces. The scheduled state transition rules are associated with corresponding interfaces of the modules.

摘要翻译： 调度方法使得能够在同步系统的单个周期中调度顺序执行规则，而不需要为可能组成的每个规则序列显式地实现复合规则。 用于设计同步数字系统的一种方法包括使用具有多个连续接口的模块，使得在单个时钟周期内，每个模块执行相当于通过其接口之一完成交互的功能，然后通过其任何接口之一进行交互。 调度状态转换规则与模块的相应接口相关联。