公开(公告)号：US6092212A

公开(公告)日：2000-07-18

申请号：US996305

申请日：1997-12-22

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4072

摘要： A method and strobe circuit are provided for maintaining a strobe signal at a valid voltage level. The method includes driving the strobe signal at the valid voltage level using a first strobe driver, pre-driving the strobe signal at the valid voltage level using a second strobe driver while the first strobe driver is driving, and terminating the driving of the first strobe driver. The strobe circuit includes a strobe line, a first strobe driver having a first enable input for enabling the first strobe driver and adapted to drive the strobe line with a first strobe signal, and a second strobe driver having a second enable input for enabling the second strobe driver and adapted to drive the strobe line with a second strobe signal. A first strobe controller is coupled to the second enable input and adapted to enable the second strobe driver to pre-drive the second strobe signal while the first strobe driver is enabled, wherein the first and second strobe signals are at equal logic levels.

摘要翻译： 提供了一种用于将选通信号保持在有效电压电平的方法和选通电路。 该方法包括使用第一选通驱动器以有效电压电平驱动选通信号，在第一选通驱动器正在驱动时，使用第二选通驱动器以有效电压电平预驱动选通信号，并终止第一选通脉冲的驱动 司机。 选通电路包括选通线，第一选通驱动器具有第一使能输入，用于启用第一选通驱动器，并且适于用第一选通信号驱动选通线;以及第二选通驱动器，具有第二使能输入， 选通驱动器，并且适于用第二选通信号驱动频闪线。 第一选通控制器耦合到第二使能输入，并且适于使第二选通驱动器在第一选通驱动器被使能的同时预驱动第二选通信号，其中第一和第二选通信号处于相等的逻辑电平。

公开(公告)号：US07609091B2

公开(公告)日：2009-10-27

申请号：US11240585

申请日：2005-09-29

申请人： Harry Muljono ,  Stefan Rusu ,  Yanmei Tian ,  Mubeen Atha ,  David J. Ayers

发明人： Harry Muljono ,  Stefan Rusu ,  Yanmei Tian ,  Mubeen Atha ,  David J. Ayers

IPC分类号： H03K17/16

CPC分类号： H04L25/0276

摘要： With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.

摘要翻译： 利用本文公开的一些发射机实施例，可以降低低功率模式中的静态功耗，而不会过度增加等待时间。

公开(公告)号：US06596980B2

公开(公告)日：2003-07-22

申请号：US09944240

申请日：2001-08-31

申请人： Stefan Rusu ,  Harry Muljono ,  Gary L. Woods ,  Jeremy A. Rowlette ,  Dean J. Grannes

发明人： Stefan Rusu ,  Harry Muljono ,  Gary L. Woods ,  Jeremy A. Rowlette ,  Dean J. Grannes

IPC分类号： H01L3100

CPC分类号： G01R31/31709 ,  G01R31/311

摘要： Time-correlated photon counting is used to measure integrated circuit (IC) performance related to signal jitter (such as clock jitter) in a manner that is non-invasive to the circuit or node of interest. The signal jitter is measured by counting photon emissions at various nodes of interest across a controlled collapse chip connect (C4) mounted die, without interfering with the normal operation of the circuit of interest. This increases the precision and accuracy of the measurement of signal jitter significantly, since small amounts of phase noise on a particular clock signal edge can be detected. The emitted photons can be detected and subsequently correlated to a precise time base to obtain a statistical spread of switching events in time. The range of the photon distribution can be used to reliably determine safe and reasonable timing guard bands for clock and data paths in an IC.

摘要翻译： 时间相关光子计数用于以对感兴趣的电路或节点无创的方式测量与信号抖动（例如时钟抖动）相关的集成电路（IC）性能。 通过在受控的崩溃芯片连接（C4）安装的管芯上计算感兴趣的各个节点处的光子发射来测量信号抖动，而不干扰感兴趣的电路的正常操作。 这可以显着提高信号抖动测量的精度和精度，因为可以检测到特定时钟信号边沿上的少量相位噪声。 发射的光子可以被检测并随后与精确的时基相关联，以及时获得切换事件的统计扩展。 光子分布的范围可用于可靠地确定IC中时钟和数据路径的安全合理的定时保护带。

公开(公告)号：US6044417A

公开(公告)日：2000-03-28

申请号：US2140

申请日：1997-12-31

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F13/40 ,  G06F13/10

CPC分类号： G06F13/4022 ,  Y02B60/1228 ,  Y02B60/1235

摘要： In one aspect of the present invention, a bus buffer is provided. The bus buffer includes at least one buffer group having first and second groups of control input terminals. The first and second groups of control input terminals control different operational characteristics of the buffer group. The bus buffer includes first and second capture registers and first and second update registers. The data output terminals of the first update register are connected to the first group of control input terminals. The data output terminals of the second update register are coupled to the second group of control input terminals. The data input terminals of the first and second update registers are coupled to the data output terminals of the first and second capture registers, respectively. The bus buffer includes a new settings register having data output terminals coupled to the data input terminals of the capture registers.

摘要翻译： 在本发明的一个方面，提供一种总线缓冲器。 总线缓冲器包括具有第一组和第二组控制输入端的至少一个缓冲器组。 第一组和第二组控制输入端控制缓冲组的不同操作特性。 总线缓冲器包括第一和第二捕捉寄存器以及第一和第二更新寄存器。 第一更新寄存器的数据输出端子连接到第一组控制输入端子。 第二更新寄存器的数据输出端耦合到第二组控制输入端。 第一和第二更新寄存器的数据输入端分别耦合到第一和第二捕获寄存器的数据输出端。 总线缓冲器包括具有耦合到捕获寄存器的数据输入端的数据输出端的新设置寄存器。

公开(公告)号：US07669069B2

公开(公告)日：2010-02-23

申请号：US11477186

申请日：2006-06-28

申请人： Stefan Rusu ,  Harry Muljono ,  Alex Kuperman

发明人： Stefan Rusu ,  Harry Muljono ,  Alex Kuperman

IPC分类号： G06F1/32

CPC分类号： G06F1/3209 ,  H04L49/90

摘要： A system may include detection of a logical mode of a link port, and changing of a link supply power provided to the link port based on the detected logical mode. Detection of the logical mode may include a determination of whether the link port is terminated by a partner link port. If the link port is not terminated, the link supply power may be reduced to a value that does not preserve logic states of a plurality of link port elements, and, if the link port is terminated, the link supply power may be maintained substantially at Vcc.

摘要翻译： 系统可以包括检测链路端口的逻辑模式，以及基于检测到的逻辑模式改变提供给链路端口的链路供电功率。 逻辑模式的检测可以包括确定链路端口是否被对方链路端口终止。 如果链路端口没有被终止，则链路供电功率可以减小到不保留多个链路端口元件的逻辑状态的值，并且如果链路端口被终止，链路供电功率可以基本维持在 Vcc。

公开(公告)号：US20080059815A1

公开(公告)日：2008-03-06

申请号：US11477186

申请日：2006-06-28

申请人： Stefan Rusu ,  Harry Muljono ,  Alex Kuperman

发明人： Stefan Rusu ,  Harry Muljono ,  Alex Kuperman

IPC分类号： G06F1/00

CPC分类号： G06F1/3209 ,  H04L49/90

摘要： A system may include detection of a logical mode of a link port, and changing of a link supply power provided to the link port based on the detected logical mode. Detection of the logical mode may include a determination of whether the link port is terminated by a partner link port. If the link port is not terminated, the link supply power may be reduced to a value that does not preserve logic states of a plurality of link port elements, and, if the link port is terminated, the link supply power may be maintained substantially at Vcc.

摘要翻译： 系统可以包括检测链路端口的逻辑模式，以及基于检测到的逻辑模式改变提供给链路端口的链路供电功率。 逻辑模式的检测可以包括确定链路端口是否被对方链路端口终止。 如果链路端口没有被终止，则链路供电功率可以减小到不保留多个链路端口元件的逻辑状态的值，并且如果链路端口被终止，链路供电功率可以基本维持在 V cc。

公开(公告)号：US06507182B2

公开(公告)日：2003-01-14

申请号：US09750131

申请日：2000-12-29

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G01R2900

CPC分类号： G01R31/311 ,  G01R29/02 ,  G01R31/31725

摘要： A non-invasive method and apparatus accurately measures the time difference between two signal edges by optically detecting the emission from a ‘beacon device’ that is modulated as a function of time difference. Through the use of this modulation it is possible to perform timing measurement accurately. Embodiments of a voltage modulator circuit modulate timing information into emission intensity. The method and system of the present invention can be used in applications such as clock skew and pulse width measurements.

公开(公告)号：US20140184349A1

公开(公告)日：2014-07-03

申请号：US13730629

申请日：2012-12-28

申请人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

发明人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

IPC分类号： H03K7/02

CPC分类号： H03K7/02

摘要： Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

摘要翻译： 用于配置逻辑以实现信号调制的技术和机制。 在一个实施例中，逻辑包括包括电路的有限脉冲响应（FIR）模块。 选择电路可以用于同时从FIR模块的锁存电路接收信号，并且基于该信号来选择选择电路的输入组并输出电压标识符。 在另一个实施例中，配置逻辑可操作以设置操作模式，其确定由FIR模块接收的并发输入信号的总数，FIR模块将使用该模式来选择用于生成表示电压电平的输出的输入组。

公开(公告)号：US07069455B2

公开(公告)日：2006-06-27

申请号：US10611079

申请日：2003-06-30

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F1/26 ,  H03K3/00

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292 ,  Y02D30/30

摘要： A driver of a first component and a receiver of a second component of a system are equipped to operate at least one of the driver and the receiver in a low power consumption state, during at least a portion of a quiescent state, when transmitting data from the first to the second component differentially, via a link interface with two lines, coupling the components. The driver and the receiver include respective monitor circuits to detect for the quiescent state, with the driver's monitor circuit monitoring for constancy over a predetermined period, and the receiver's monitor circuit monitoring for zero states on both lines. Further, in one embodiment, the driver's monitor circuit places the driver in the low power consumption state by grounding the two lines.

摘要翻译： 在系统的第二部件的第一部件和接收器的驱动器被配备为在静止状态的至少一部分期间以低功耗状态操作驱动器和接收器中的至少一个，当从 第一个到第二个组件差别化，通过一个具有两条线的链接界面，耦合这些组件。 驱动器和接收器包括用于检测静止状态的各个监视器电路，其中驾驶员的监视器电路在预定时间段内监视恒定状态，并且接收器的监视器电路监视两条线路上的零状态。 此外，在一个实施例中，驾驶员监视器电路通过使两条线路接地来将驾驶员置于低功耗状态。

公开(公告)号：US06707118B2

公开(公告)日：2004-03-16

申请号：US10298756

申请日：2002-11-18

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： H01L2994

CPC分类号： H01L27/08 ,  H01L27/0794 ,  H01L27/0802 ,  H01L29/7841 ,  H01L29/78612

摘要： A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

摘要翻译： 半导体器件可以形成有位于半导体结构中的绝缘体上方的浮动体。 门可以形成在浮体上方但与之隔开。 半导体结构可以包括围绕浮体的掺杂区域。浮体沿其长度提供分布的电容和电阻以形成集成的RC电路。 电阻的程度是浮体沿着源区和漏极区的横截面面积的函数，其电容是掺杂区与体之间以及栅与体之间的间隔的函数。 在本发明的一些实施例中，可以实现对输入电压变化的补偿。