Checkpointing a superscalar, out-of-order processor for error recovery
    1.
    发明授权
    Checkpointing a superscalar, out-of-order processor for error recovery 有权
    检查一个超标量,无序处理器进行错误恢复

    公开(公告)号:US06968476B2

    公开(公告)日:2005-11-22

    申请号:US10180385

    申请日:2002-06-26

    摘要: The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache (66) via a Store Buffer (65) and an Architected Register Array (ARA) (64) is provided which is based on the youngest instruction ID (40) stored in the Checkpoint State Buffer (CSB) (60).

    摘要翻译: 本发明涉及从给定检查点内置错误恢复的数据处理系统。 为了对每个周期的多于一个指令进行检查,建议收集用于检查点状态的缓冲器(CSB)(60)中的相应多个CISC / RISC指令执行的预定最大数量的寄存器内容的更新,由此检查点 状态包括与所述多个CISC指令相对应的寄存器可更新的缓冲器槽,以及与所述多个最小外部指令相关联的程序计数器值的条目,并且以新鲜的方式更新建筑物寄存器阵列(ARA)(64) 在完成所述多个外部指令的所述最小外部指令之后确定在所述寄存器数据中没有检测到错误之后,收集的寄存器数据。 提供握手同步,用于通过存储缓冲器(65)和架构化寄存器阵列(ARA)(64)存储在L2高速缓存(66)中的一致更新,其基于存储在检查点中的最年轻的指令ID(40) 状态缓冲区(CSB)(60)。

    Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme
    2.
    发明授权
    Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme 失效
    在两级表方案中使用基于步幅的模式历史和最终值预测的通用负载地址/值预测

    公开(公告)号:US06986027B2

    公开(公告)日:2006-01-10

    申请号:US09864590

    申请日:2001-05-24

    IPC分类号: G06F9/34 G06F9/44

    摘要: This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as context prediction, without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table. Thus, a last value prediction can be achieved by predicting a ‘pattern’ of just one stride equal to zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modeled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme is inherently included in the system itself and operates basically by immediate evaluation of counters in the pattern history table.

    摘要翻译: 本发明是用于混合预测负载地址和/或值的方法和系统。 新的价值预测方案基于最后的价值和步幅以及上下文预测提供预测,而不需要在几个预测变量之间使用复杂的交换方案。 系统在第一个表中收集后续值的三角形的模式,而不是值本身。 因此,可以通过预测等于零的一个步幅的“模式”来实现最后的值预测。 步幅预测器使用一个恒定步幅的图案。 并且通过在值之间记录三角形的模式并将三角形添加到最后一个值来建模特定的值模式。 交换方案固有地包含在系统本身中,并且基本上通过对模式历史表中的计数器的立即评估来进行操作。