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30 条记录 (耗时 0.036 秒)

    PLL circuit having loop filter and method of driving the same
    1.
    发明申请
    PLL circuit having loop filter and method of driving the same 有权
    具有环路滤波器的PLL电路及其驱动方法

    公开(公告)号：US20080068058A1

    公开(公告)日：2008-03-20

    申请号：US11822103

    申请日：2007-07-02

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/085 ,  H03L7/08

    CPC分类号： H03L7/093 ,  H03L7/10

    摘要： A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.

    摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，并产生上拉控制信号和下拉控制信号。 环路滤波器根据上拉和下拉控制信号抽取电压，对泵浦电压进行滤波，并输出一个控制电压。 压控振荡器接收控制信号并振荡输出时钟。 时钟分频器以预定速率分频输出时钟的频率，以产生反馈时钟。 在PLL电路中，环路滤波器包括用于补偿变化的补偿器。

    Phase detecting circuit and clock generating apparatus including the same
    2.
    发明授权
    Phase detecting circuit and clock generating apparatus including the same 有权
    相位检测电路和包括该相位检测电路的时钟发生装置

    公开(公告)号：US07949081B2

    公开(公告)日：2011-05-24

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/04 ,  H03L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME
    3.
    发明申请
    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME 有权
    相位检测电路和时钟发生装置，包括它们

    公开(公告)号：US20090097608A1

    公开(公告)日：2009-04-16

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

    PLL circuit and method of controlling the same
    5.
    发明申请
    PLL circuit and method of controlling the same 失效
    PLL电路及其控制方法

    公开(公告)号：US20080068057A1

    公开(公告)日：2008-03-20

    申请号：US11819603

    申请日：2007-06-28

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/085 ,  H03L7/08

    CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/10

    摘要： A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.

    摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，以产生上拉和下拉控制信号。 低通滤波器响应于上拉和下拉控制信号泵送电压，并从泵浦电压中去除噪声分量，以输出控制电压。 控制电压以产生具有比控制电压更小的摆动宽度的偏置电压的缓冲器。 压控振荡器接收偏置电压并振荡输出时钟。 时钟分频器以预定的比例对输出时钟的频率进行分频，以产生反馈时钟。