公开(公告)号：US20070278531A1

公开(公告)日：2007-12-06

申请号：US11648057

申请日：2006-12-29

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42336

摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

摘要翻译： 半导体闪存器件。 闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。 栅极绝缘膜介于浮栅电极和半导体衬底之间。 控制栅电极设置在浮栅电极上。 浮栅电极包括与凹部的倾斜侧相邻的突起。

公开(公告)号：US07642593B2

公开(公告)日：2010-01-05

申请号：US11698658

申请日：2007-01-26

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

公开(公告)号：US07531410B2

公开(公告)日：2009-05-12

申请号：US11648057

申请日：2006-12-29

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42336

摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

摘要翻译： 半导体闪存器件。 闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。 栅极绝缘膜介于浮栅电极和半导体衬底之间。 控制栅电极设置在浮栅电极上。 浮栅电极包括与凹部的倾斜侧相邻的突起。

公开(公告)号：US20070170491A1

公开(公告)日：2007-07-26

申请号：US11698658

申请日：2007-01-26

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

公开(公告)号：US07602008B2

公开(公告)日：2009-10-13

申请号：US11957037

申请日：2007-12-14

申请人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

发明人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

IPC分类号： H01L27/115

CPC分类号： H01L29/7887 ,  H01L29/66825

摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

摘要翻译： 公开了用于制造非易失性存储器件的非易失性存储器件和方法。 更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

公开(公告)号：US07320913B2

公开(公告)日：2008-01-22

申请号：US11368247

申请日：2006-03-03

申请人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

发明人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L29/7885 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

摘要翻译： 公开了用于制造非易失性存储器件的非易失性存储器件和方法。 更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

公开(公告)号：US07973314B2

公开(公告)日：2011-07-05

申请号：US12117630

申请日：2008-05-08

申请人： Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Yong-Suk Choi ,  Hyok-Ki Kwon

发明人： Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Yong-Suk Choi ,  Hyok-Ki Kwon

IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L27/105 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.

摘要翻译： 半导体器件具有第一半导体层，其包括第一电路，设置在第一半导体层上并具有第二电路的第二半导体层，以及延伸穿过第一和第二半导体层的部分的通孔，并且第一半导体层和第二电路 电连接。 电路中的一个是逻辑电路，另一个电路是存储器电路。 半导体器件通过在各个衬底上制造逻辑电路和存储器电路的晶体管，堆叠衬底以及将逻辑电路和存储器电路与通孔电连接来制造。

公开(公告)号：US07855410B2

公开(公告)日：2010-12-21

申请号：US12168799

申请日：2008-07-07

申请人： Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Suk Choi ,  Hyok-Ki Kwon ,  Bae-Seong Kwon

发明人： Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Suk Choi ,  Hyok-Ki Kwon ,  Bae-Seong Kwon

IPC分类号： H01L29/788

CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

摘要： According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，半导体存储器件的一般特征可以包括在半导体衬底上的栅极绝缘层，栅极绝缘层上的浮动栅极和设置在浮动栅极一侧的字线。 面对字线的浮动栅极的第一侧可以包括朝向字线突出的突出部分。 突出部分的尖端可以包括相对于半导体衬底的顶表面基本垂直地延伸的角部。

公开(公告)号：US20080093647A1

公开(公告)日：2008-04-24

申请号：US11957037

申请日：2007-12-14

申请人： Sung-Taeg KANG ,  Hyok-Ki Kwon ,  Bo Seo ,  Seung Yoon ,  Hee Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

发明人： Sung-Taeg KANG ,  Hyok-Ki Kwon ,  Bo Seo ,  Seung Yoon ,  Hee Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L29/66825

摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

摘要翻译： 公开了用于制造非易失性存储器件的非易失性存储器件和方法。 更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

公开(公告)号：US20060199336A1

公开(公告)日：2006-09-07

申请号：US11368247

申请日：2006-03-03

申请人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Seo ,  Seung Yoon ,  Hee Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

发明人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Seo ,  Seung Yoon ,  Hee Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L29/7885 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

摘要翻译： 公开了用于制造非易失性存储器件的非易失性存储器件和方法。 更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。