公开(公告)号：US06657916B2

公开(公告)日：2003-12-02

申请号：US10054195

申请日：2002-01-22

申请人： Heinz Hönigschmid ,  Stefan Lammers ,  Helmut Kandolf

发明人： Heinz Hönigschmid ,  Stefan Lammers ,  Helmut Kandolf

IPC分类号： G11C800

CPC分类号： G11C8/00 ,  G11C8/08

摘要： An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

摘要翻译： 集成存储器具有存储单元阵列，其存储单元连接到字线和位线。 为了从一个存储单元读取或写入存储单元，第一字线可以通过可控的第一开关器件连接到电源电路，并且第二字线可以经由可控的第二开关器件连接到电源电路 。 根据第一字线的激活状态，控制电路可以根据第二字线和第二开关器件的激活状态来驱动第一开关器件。 因此，当前未使用的现有字线可用于寻址存储单元之一。 结果，字线只需要一个接线面。

公开(公告)号：US06816406B2

公开(公告)日：2004-11-09

申请号：US10715023

申请日：2003-11-17

申请人： Heinz Hönigschmid ,  Helmut Kandolf ,  Stefan Lammers

发明人： Heinz Hönigschmid ,  Helmut Kandolf ,  Stefan Lammers

IPC分类号： G11C1114

CPC分类号： G11C11/16

摘要： A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

公开(公告)号：US06445607B2

公开(公告)日：2002-09-03

申请号：US09829288

申请日：2001-04-09

申请人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

发明人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

摘要翻译： 给出了一种用于操作具有存储单元的集成存储器的方法，每个存储单元都具有选择晶体管和具有铁电存储效应的存储电容器。 存储器包含板线，其经由包含各个存储器单元的选择晶体管和存储电容器的串联电路连接到列线之一。 根据“脉冲板概念”进行记忆存取。 在这种情况下，以这样的方式控制时间序列，使得在访问周期中，要选择的存储单元的存储电容器在每种情况下都以相同的量被放电。 因此避免了由未激活的选择晶体管的源漏泄漏电流引起的存储在存储单元中的信息的衰减或破坏。

公开(公告)号：US06577528B2

公开(公告)日：2003-06-10

申请号：US10023155

申请日：2001-12-17

申请人： Dietmar Gogl ,  Helmut Kandolf ,  Heinz Hönigschmid

发明人： Dietmar Gogl ,  Helmut Kandolf ,  Heinz Hönigschmid

IPC分类号： G11C1100

CPC分类号： G11C8/12 ,  G11C11/15

摘要： A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

公开(公告)号：US06515890B2

公开(公告)日：2003-02-04

申请号：US09780305

申请日：2001-02-09

申请人： Robert Esterl ,  Helmut Kandolf ,  Heinz Hönigschmid ,  Thomas Röhr

发明人： Robert Esterl ,  Helmut Kandolf ,  Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

摘要翻译： 集成半导体存储器具有具有铁电存储器特性的存储单元。 存储器单元在每种情况下都连接在列线和充电线之间。 列线连接到提供输出信号的读取放大器。 充电线连接到向给定电位提供充电线的驱动器电路。 在非活动模式下，列线和充电线在读取放大器或驱动电路中共同连接到用于共同供电电位的连接。 结果，线之间的电位的相对快速的均衡是可能的。 因此，避免了由于干扰电压引起的存储器单元内容的意外变化。

公开(公告)号：US06538950B2

公开(公告)日：2003-03-25

申请号：US09917553

申请日：2001-07-27

申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Stefan Lammers ,  Thomas Rohr

发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Stefan Lammers ,  Thomas Rohr

IPC分类号： G11C800

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/1006

摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

公开(公告)号：US06353562B2

公开(公告)日：2002-03-05

申请号：US09780326

申请日：2001-02-09

申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

IPC分类号： G11C700

CPC分类号： G11C29/24 ,  G11C29/787

摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

摘要翻译： 集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。 此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。 冗余电路用于选择冗余单元。 处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。 在冗余电路中编写修复信息之前，可以对冗余单元进行测试。 所需的电路复杂度相对较低。

公开(公告)号：US06741513B2

公开(公告)日：2004-05-25

申请号：US10001176

申请日：2001-11-02

申请人： Heinz Hönigschmid ,  Gerhard Müller

发明人： Heinz Hönigschmid ,  Gerhard Müller

IPC分类号： G11C800

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

摘要： The data memory has a plurality of banks, each with a multiplicity of memory cells that form a matrix of rows and columns with respectively assigned matrix row lines and column lines. The banks are arranged spatially one on top of the other as stacks, with the stack edges that are parallel to the matrix rows and at which the ends of the column lines that are connected to a respective column-driving device are located, lie in a common plane. The common plane extends in the direction of the matrix rows and is substantially orthogonal with respect to the direction of the columns. The column-driving devices of all the banks are arranged directly adjacent to one another as a block in the direction of the columns, on or near the same edge of the bank stack. The banks preferably contain memory cells which can be read out without damage, and in each case a plurality of column lines are each assigned to one common sense amplifier in the column-driving device of each bank.

摘要翻译： 数据存储器具有多个存储体，每个存储体具有多个存储单元，其形成具有分配矩阵行行和列线的行和列的矩阵。 这些组在空间上以一堆叠的方式布置在堆叠中，堆叠边缘平行于矩阵行，并且连接到相应列驱动装置的列线的端部位于其中，位于 普通飞机 公共平面在矩阵行的方向上延伸并且相对于列的方向基本正交。 所有的列的列驱动装置被布置成彼此直接相邻的列，在列的方向上，在或者在该组堆的同一边缘附近。 这些存储体优选地包含可以被读取而不损坏的存储单元，并且在每种情况下，多个列线分别被分配给每个存储体的列驱动装置中的一个常读放大器。

公开(公告)号：US06507512B2

公开(公告)日：2003-01-14

申请号：US09946859

申请日：2001-09-04

申请人： Heinz Hönigschmid

发明人： Heinz Hönigschmid

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C29/50

摘要： A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer. A second transistor is inserted in parallel with the driver transistors, which form a first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated in a test mode.

摘要翻译： 一种用于加速MRAM中的老化的电路配置和方法，其中提供附加电路以便将更高的电流馈送到位于更靠近软磁层的存储单元的控制线中。 第二晶体管与驱动晶体管并联插入，形成第一控制单元。 第二晶体管通过位于更靠近软磁层的控制线提供电流。 第二晶体管可以通过控制线驱动更高的电流，并且可以在测试模式下被激活。

公开(公告)号：US06664158B2

公开(公告)日：2003-12-16

申请号：US10034931

申请日：2001-11-21

申请人： Christine Dehm ,  Heinz Hönigschmid ,  Thomas Röhr

发明人： Christine Dehm ,  Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.