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38 条记录 (耗时 0.02 秒)

    Data memory with a plurality of memory banks
    1.
    发明授权
    Data memory with a plurality of memory banks 失效
    具有多个存储体的数据存储器

    公开(公告)号：US06741513B2

    公开(公告)日：2004-05-25

    申请号：US10001176

    申请日：2001-11-02

    申请人： Heinz Hönigschmid ,  Gerhard Müller

    发明人： Heinz Hönigschmid ,  Gerhard Müller

    IPC分类号： G11C800

    CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

    摘要： The data memory has a plurality of banks, each with a multiplicity of memory cells that form a matrix of rows and columns with respectively assigned matrix row lines and column lines. The banks are arranged spatially one on top of the other as stacks, with the stack edges that are parallel to the matrix rows and at which the ends of the column lines that are connected to a respective column-driving device are located, lie in a common plane. The common plane extends in the direction of the matrix rows and is substantially orthogonal with respect to the direction of the columns. The column-driving devices of all the banks are arranged directly adjacent to one another as a block in the direction of the columns, on or near the same edge of the bank stack. The banks preferably contain memory cells which can be read out without damage, and in each case a plurality of column lines are each assigned to one common sense amplifier in the column-driving device of each bank.

    摘要翻译： 数据存储器具有多个存储体，每个存储体具有多个存储单元，其形成具有分配矩阵行行和列线的行和列的矩阵。 这些组在空间上以一堆叠的方式布置在堆叠中，堆叠边缘平行于矩阵行，并且连接到相应列驱动装置的列线的端部位于其中，位于 普通飞机 公共平面在矩阵行的方向上延伸并且相对于列的方向基本正交。 所有的列的列驱动装置被布置成彼此直接相邻的列，在列的方向上，在或者在该组堆的同一边缘附近。 这些存储体优选地包含可以被读取而不损坏的存储单元，并且在每种情况下，多个列线分别被分配给每个存储体的列驱动装置中的一个常读放大器。

    Circuit configuration and method for accelerating aging in an MRAM
    2.
    发明授权
    Circuit configuration and method for accelerating aging in an MRAM 失效
    MRAM加速老化的电路配置和方法

    公开(公告)号：US06507512B2

    公开(公告)日：2003-01-14

    申请号：US09946859

    申请日：2001-09-04

    申请人： Heinz Hönigschmid

    发明人： Heinz Hönigschmid

    IPC分类号： G11C1100

    CPC分类号： G11C11/16 ,  G11C29/50

    摘要： A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer. A second transistor is inserted in parallel with the driver transistors, which form a first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated in a test mode.

    摘要翻译： 一种用于加速MRAM中的老化的电路配置和方法，其中提供附加电路以便将更高的电流馈送到位于更靠近软磁层的存储单元的控制线中。 第二晶体管与驱动晶体管并联插入，形成第一控制单元。 第二晶体管通过位于更靠近软磁层的控制线提供电流。 第二晶体管可以通过控制线驱动更高的电流，并且可以在测试模式下被激活。

    Method for operating an integrated memory
    3.
    发明授权
    Method for operating an integrated memory 失效
    操作集成存储器的方法

    公开(公告)号：US06445607B2

    公开(公告)日：2002-09-03

    申请号：US09829288

    申请日：2001-04-09

    申请人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

    发明人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

    摘要翻译： 给出了一种用于操作具有存储单元的集成存储器的方法，每个存储单元都具有选择晶体管和具有铁电存储效应的存储电容器。 存储器包含板线，其经由包含各个存储器单元的选择晶体管和存储电容器的串联电路连接到列线之一。 根据“脉冲板概念”进行记忆存取。 在这种情况下，以这样的方式控制时间序列，使得在访问周期中，要选择的存储单元的存储电容器在每种情况下都以相同的量被放电。 因此避免了由未激活的选择晶体管的源漏泄漏电流引起的存储在存储单元中的信息的衰减或破坏。

    Fuse circuit configuration
    5.
    发明授权
    Fuse circuit configuration 有权
    保险丝电路配置

    公开(公告)号：US06545526B2

    公开(公告)日：2003-04-08

    申请号：US09867257

    申请日：2001-05-29

    申请人： Heinz Hönigschmid

    发明人： Heinz Hönigschmid

    IPC分类号： H01H3776

    CPC分类号： G11C17/14 ,  G11C17/18

    摘要： A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

    摘要翻译： 描述了一种熔断器电路结构，其中补偿电容器抵消寄生电容器。 寄生电容发生在开关晶体管的连接点和保险丝与地之间。 补偿电容器连接到评估电路。 以这种方式，补偿由寄生电容器引起的负面影响。

    Circuit configuration for reading a memory cell having a ferroelectric capacitor
    8.
    发明授权
    Circuit configuration for reading a memory cell having a ferroelectric capacitor 有权
    用于读取具有铁电电容器的存储单元的电路配置

    公开(公告)号：US06434039B1

    公开(公告)日：2002-08-13

    申请号：US09838750

    申请日：2001-04-19

    申请人： Georg Braun ,  Heinz Hönigschmid

    发明人： Georg Braun ,  Heinz Hönigschmid

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.

    摘要翻译： 描述用于读取具有铁电电容器的铁电存储单元的电路结构。 存储单元连接到位线。 电路配置提供了具有第一差分放大器输入，第二差分放大器输入和差分放大器输出的差分放大器。 第一差分放大器输入连接到位线，第二差分放大器输入连接到参考信号。 第一驱动电路的第一驱动器输入端连接到差分放大器输出，第一驱动器输出端连接到位线。 差分放大器通过第一驱动电路反馈，并将位线电压调节到参考信号的电压值。

    Integrated memory with redundancy and method for repairing an integrated memory
    9.
    发明授权
    Integrated memory with redundancy and method for repairing an integrated memory 失效

    公开(公告)号：US06396750B2

    公开(公告)日：2002-05-28

    申请号：US09888022

    申请日：2001-06-22

    申请人： Heinz Hönigschmid ,  Georg Braun ,  Andrej Majdic

    发明人： Heinz Hönigschmid ,  Georg Braun ,  Andrej Majdic

    IPC分类号： G11C700

    CPC分类号： G11C29/78 ,  G11C29/702

    摘要： An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.