High performance chipset prefetcher for interleaved channels
    1.
    发明申请
    High performance chipset prefetcher for interleaved channels 有权
    用于交错通道的高性能芯片组预取器

    公开(公告)号:US20070005934A1

    公开(公告)日:2007-01-04

    申请号:US11172401

    申请日:2005-06-29

    IPC分类号: G06F12/00

    摘要: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

    摘要翻译: 本发明包括一种从具有交织信道的存储装置预取的装置和方法。 芯片组预取器包括用于检测流中的步幅的步幅检测器,用于将预取插入存储器件的预取注入器,用于将预取映射到存储器件的每个通道的通道映射器,调度器以将预取计划到存储器上 DRAM状态感知方式的设备,限制预取数量的限制启发式,以及预取数据缓冲器来存储预取数据。 预取方法包括跟踪流的状态,检测一条流上的步幅,选择用于预取注入的步幅的流,从所选择的流中引入预取,将预取映射到每个交错通道,注入预取 从所选择的流到每个交织的信道,并且以DRAM状态感知的方式将预取调度到存储器设备上。

    Early global observation point for a uniprocessor system
    2.
    发明申请
    Early global observation point for a uniprocessor system 审中-公开
    早期全球观察点的单处理器系统

    公开(公告)号:US20070073977A1

    公开(公告)日:2007-03-29

    申请号:US11241363

    申请日:2005-09-29

    IPC分类号: G06F13/28

    CPC分类号: G06F12/0835

    摘要: In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括一种用于在单处理器系统的处理器中执行操作的方法,发起写入事务以将操作结果发送到单处理器系统的存储器,以及发出用于写入的全局观察点 事务处理器之前,将结果写入内存。 在一些实施例中,全局观测点可以比处理器处于多处理器系统中的情况更早发布。 描述和要求保护其他实施例。

    Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
    3.
    发明申请
    Multi-node chipset lock flow with peer-to-peer non-posted I/O requests 有权
    具有点对点非贴片I / O请求的多节点芯片组锁定流

    公开(公告)号:US20050273400A1

    公开(公告)日:2005-12-08

    申请号:US10859891

    申请日:2004-06-02

    IPC分类号: G06F17/60

    CPC分类号: G06F13/387 G06Q10/087

    摘要: Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.

    摘要翻译: 管理事务的系统和方法提供在第一I / O集线器处接收第一冲洗命令,其中第一冲洗命令专用于未发布的事务。 一个实施例进一步提供响应于第一冲洗命令而停止关于非发布的事务的第一I / O集线器的入站订购队列,并将未发布的事务从第一I / O集线器的输出缓冲器刷新到 第二个I / O中枢,而对于未发布的事务,入站订购队列被停止。