公开(公告)号：US20080005303A1

公开(公告)日：2008-01-03

申请号：US11479386

申请日：2006-06-30

申请人： Hemant Rotithor ,  An-Chow Lai

发明人： Hemant Rotithor ,  An-Chow Lai

IPC分类号： G06F15/173

CPC分类号： H04L43/16 ,  H04L41/0896 ,  H04L43/0882

摘要： A method is described that involves determining that utilization of a logical link has reached a first threshold. The logical link comprises a first number of active physical links. The method also involves inactivating one or more of the physical links to produce a second number of active physical links. The second number is less than the first number. The method also involves determining that the second number of active physical links have not been utilized for a period of time and inactivating another set of links.

摘要翻译： 描述了涉及确定逻辑链路的利用率已经达到第一阈值的方法。 逻辑链路包括第一数量的活动物理链路。 该方法还涉及使一个或多个物理链路失活以产生第二数量的活动物理链路。 第二个数字小于第一个数字。 该方法还涉及确定第二数量的活动物理链路未被使用一段时间并且使另一组链路失效。

公开(公告)号：US20070005934A1

公开(公告)日：2007-01-04

申请号：US11172401

申请日：2005-06-29

申请人： Hemant Rotithor ,  Abhishek Singhal ,  Randy Osborne ,  Zohar Bogin ,  Raul Gutierrez ,  Buderya Acharya ,  Surya Kareenahalli

发明人： Hemant Rotithor ,  Abhishek Singhal ,  Randy Osborne ,  Zohar Bogin ,  Raul Gutierrez ,  Buderya Acharya ,  Surya Kareenahalli

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F12/0607 ,  G06F2212/6022 ,  G06F2212/6026

摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

摘要翻译： 本发明包括一种从具有交织信道的存储装置预取的装置和方法。 芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。 预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取 从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。

公开(公告)号：US20050204094A1

公开(公告)日：2005-09-15

申请号：US10877356

申请日：2004-06-25

申请人： Hemant Rotithor ,  Randy Osborne

发明人： Hemant Rotithor ,  Randy Osborne

IPC分类号： G06F12/00

CPC分类号： G06F13/1668 ,  G06F12/0215 ,  G06F12/0607 ,  G06F12/0804 ,  G11C15/00

摘要： Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same rank, bank and page; select and transmit write commands from one chain at a time until each chain is done; and select a next chain of write commands to transmit, while creating and using a write page closing hint to determine when a change between pages of a given rank and bank should bring about the preemptive closing of a page to minimize incidents of incurring lengthy page miss delays.

摘要翻译： 接收新的写事务请求的装置和方法; 将已经存储的订单，新请求的页面和页面与对同一等级，银行和页面的写入命令的组合链进行比较; 一次从一个链中选择和发送写入命令，直到每个链完成; 并选择下一个写入命令链以传输，同时创建和使用写入页面关闭提示来确定给定等级和银行的页面之间的更改是否应该引起页面的抢先关闭，以最大限度地减少发生冗长页面错误的事件 延误

公开(公告)号：US20050091460A1

公开(公告)日：2005-04-28

申请号：US10692245

申请日：2003-10-22

申请人： Hemant Rotithor ,  Randy Osborne ,  Nagi Aboulenein

发明人： Hemant Rotithor ,  Randy Osborne ,  Nagi Aboulenein

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1631

摘要： Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

摘要翻译： 本发明的实施例提供了一种用于将读取和写入事务调度到存储器的算法，以改进命令和数据总线利用率并在一系列工作负载上获得性能的算法。 特别地，存储器事务被排序成队列，使得它们不具有彼此的页冲突，并且根据读和写调度算法从这些队列排序排序以优化等待时间。

公开(公告)号：US10069711B2

公开(公告)日：2018-09-04

申请号：US11479386

申请日：2006-06-30

申请人： Hemant Rotithor ,  An-Chow Lai

发明人： Hemant Rotithor ,  An-Chow Lai

IPC分类号： G06F1/00 ,  H04L12/26 ,  H04L12/24

摘要： A method is described that involves determining that utilization of a logical link has reached a first threshold. The logical link comprises a first number of active physical links. The method also involves inactivating one or more of the physical links to produce a second number of active physical links. The second number is less than the first number. The method also involves determining that the second number of active physical links have not been utilized for a period of time and inactivating another set of links.

公开(公告)号：US20050204093A1

公开(公告)日：2005-09-15

申请号：US10801201

申请日：2004-03-15

申请人： Hemant Rotithor ,  Randy Osborne

发明人： Hemant Rotithor ,  Randy Osborne

IPC分类号： G06F12/00

CPC分类号： G06F12/0215 ,  G06F13/1673

摘要： Apparatus and method to select write transactions and to selectively mark a write transaction with a page closing hint to cause the page in a memory device to which the write transaction is directed to be closed immediately after the write transaction is carried out if no other write transaction is found in a buffer of pending write transactions that is directed to the same rank, bank and page to minimize incidents of incurring lengthy page miss delays.

摘要翻译： 选择写事务的装置和方法，以及如果没有其他写事务，则在执行写事务之后，使用页关闭提示来选择性地标记写事务，以使得在写事务被定向到的存储器设备中的页被立即关闭 在等待写入交易的缓冲区中找到，该缓冲区被定向到相同的等级，银行和页面，以最小化发生长时间的页面错误延迟的事件。

公开(公告)号：US20050172091A1

公开(公告)日：2005-08-04

申请号：US10769201

申请日：2004-01-29

申请人： Hemant Rotithor ,  An-Chow Lai ,  Randy Osborne ,  Olivier Maquelin ,  Mladenko Vukic

发明人： Hemant Rotithor ,  An-Chow Lai ,  Randy Osborne ,  Olivier Maquelin ,  Mladenko Vukic

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/161

摘要： A method and an apparatus to process read data return has been disclosed. In one embodiment, the method includes packing a cache line of each of a number of read data returns into one or more packets, splitting each of the one or more packets into a plurality of flits, and interleaving the plurality of flits of each of the plurality of read data returns. Other embodiments are described and claimed.

摘要翻译： 已经公开了一种处理读取数据返回的方法和装置。 在一个实施例中，所述方法包括将多个读取数据返回中的每一个的高速缓存行打包到一个或多个分组中，将所述一个或多个分组中的每一个分解成多个分组，并交织每个 多个读取数据返回。 描述和要求保护其他实施例。