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公开(公告)号：US07558994B2
公开(公告)日：2009-07-07
申请号：US10554383
申请日：2004-04-27
IPC分类号： G01R31/28
CPC分类号： G01R31/31921
摘要： A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including “care” bits and “don't care” bits. The test vector data is then compressed by comparing corresponding bits of two or more subsequent vectors and merging the two or more vectors into a single vector representative thereof if all of the corresponding bits of the two or more vectors are found to be compatible. Compatibility of two bits is achieved if they do not have specifically incompatible or opposite values.
摘要翻译： 一种用于压缩用于测试逻辑产品的测试矢量数据的方法和装置，其中原始测试向量数据以两个或更多个比特序列的形式生成，包括“关心”位和“无关位”位。 然后通过比较两个或更多个后续向量的相应比特来压缩测试向量数据，并且如果发现两个或更多个向量的所有相应比特是兼容的，则将两个或更多个向量合并成其代表的单个向量。 如果两个位没有特别不兼容或相反的值，则可实现两位的兼容性。
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公开(公告)号：US08281197B2
公开(公告)日：2012-10-02
申请号：US12092186
申请日：2006-10-23
IPC分类号： G01R31/28
CPC分类号： G01R31/318364 , G01R31/318357
摘要： A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (210); providing the simulation model with a plurality of test patterns (220); receiving a plurality of simulated test responses to said test patterns (230); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (240); providing the integrated circuit with a further plurality of test patterns (250); receiving a plurality of test responses to said further plurality of test patterns (260); and checking the plurality of responses for the presence of the signature (270). This method provides improved fault detectability for an IC subjected thereto.
摘要翻译： 一种用于在集成电路（100）中定位故障的方法（200），所述集成电路（100）具有耦合到所述集成电路的测试模式中的压缩逻辑（140）的多个数字输出，所述压缩逻辑包括用于提供测试的至少一个输出 回应被披露。 该方法包括以下步骤：提供集成电路（210）的仿真模型; 向所述仿真模型提供多个测试图案（220）; 接收对所述测试图案（230）的多个模拟测试响应; 在所述多个响应中定义多个比特，所述比特定义所述故障的签名（240）; 向所述集成电路提供另外多个测试图案（250）; 接收对所述另外多个测试图案（260）的多个测试响应; 以及检查所述多个响应中是否存在所述签名（270）。 该方法为经受其的IC提供了改进的故障检测能力。
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公开(公告)号：US20100264932A1
公开(公告)日：2010-10-21
申请号：US12063151
申请日：2006-08-09
申请人： Erik Jan Marinissen , Sandeepkumar Goel , Andre Krijn Nieuwland , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
发明人： Erik Jan Marinissen , Sandeepkumar Goel , Andre Krijn Nieuwland , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
IPC分类号： G01R31/02
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译： 集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。 集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。 保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接 并且多个的第二熔丝元件（18）处于未吹塑状态。 结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。 在测试之后，至少部分第二熔丝元件（18）被吹塑。 结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。
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公开(公告)号：US20090077439A1
公开(公告)日：2009-03-19
申请号：US12092186
申请日：2006-10-23
IPC分类号： G01R31/3177 , G06G7/62 , G06F11/25
CPC分类号： G01R31/318364 , G01R31/318357
摘要： A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (210); providing the simulation model with a plurality of test patterns (220); receiving a plurality of simulated test responses to said test patterns (230); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (240); providing the integrated circuit with a further plurality of test patterns (250); receiving a plurality of test responses to said further plurality of test patterns (260); and checking the plurality of responses for the presence of the signature (270). This method provides improved fault detectability for an IC subjected thereto.
摘要翻译： 一种用于在集成电路（100）中定位故障的方法（200），所述集成电路（100）具有耦合到所述集成电路的测试模式中的压缩逻辑（140）的多个数字输出，所述压缩逻辑包括用于提供测试的至少一个输出 回应被披露。 该方法包括以下步骤：提供集成电路（210）的仿真模型; 向所述仿真模型提供多个测试图案（220）; 接收对所述测试图案（230）的多个模拟测试响应; 在所述多个响应中定义多个比特，所述比特定义所述故障的签名（240）; 向所述集成电路提供另外多个测试图案（250）; 接收对所述另外多个测试图案（260）的多个测试响应; 以及检查所述多个响应中是否存在所述签名（270）。 该方法为经受其的IC提供了改进的故障检测能力。
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公开(公告)号：US07376873B2
公开(公告)日：2008-05-20
申请号：US10573083
申请日：2004-09-20
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31719 , G01R31/318566
摘要： An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.
摘要翻译： 公开了一种用于集成电路测试的装置。 该装置包括压缩器，用于压缩作为集成电路的一部分的被测电路的测试响应。
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6.发明授权公开(公告)号：US07293258B1
公开(公告)日：2007-11-06
申请号：US09572995
申请日：2000-05-17
申请人： Hendrikus Petrus Elisabeth Vranken , Kornelis Antonius Vissers , Fransiscus Wilhelmus Sijstermans
发明人： Hendrikus Petrus Elisabeth Vranken , Kornelis Antonius Vissers , Fransiscus Wilhelmus Sijstermans
CPC分类号： G06F11/3648
摘要： A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action is taken if one or more of the multi-bit subfields meet the corresponding conditions.
摘要翻译： 数据处理器具有调试电路，用于监视用于执行程序的操作数数据是否满足调试异常情况。 调试异常条件独立地测试向量操作数的多位子字段的两个或多个。 如果一个或多个多位子字段满足相应条件，则采取调试操作。
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公开(公告)号：US07124340B2
公开(公告)日：2006-10-17
申请号：US10091051
申请日：2002-03-05
申请人： Gerardus Arnoldus Antonius Bos , Hendrikus Petrus Elisabeth Vranken , Thomas Franciscus Waayers , David Lelouvier , Herve Fleury
发明人： Gerardus Arnoldus Antonius Bos , Hendrikus Petrus Elisabeth Vranken , Thomas Franciscus Waayers , David Lelouvier , Herve Fleury
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： In a method for testing a testable electronic device having a first and a second plurality of test a arrangements a first shift register (110) is used in parallel with a second shift register (130) to time-multiplex a first test vector (102) and a second test vector (104) into a number of smaller test vectors (102a–c; 104a–c) for provision to the first and second plurality of test arrangements. By varying the size of the first shift register (110) and the second shift register (130) a trade-off between the number of pins of the electronic device to be contacted and the required test time can be made. The first shift register (110) may be coupled to a first buffer register (120) and second shift register (130) may be coupled to a second buffer register (140) for enhanced test data stability. First shift register (110) and second shift register (130) can be partitions of a larger shift register. The method can also be used in a reverse way by time-demultiplexing test result vectors into a single vector at the output side of the testable electronic device.
摘要翻译： 在用于测试具有第一和第二多个测试的可测试电子设备的方法中，第一移位寄存器（110）与第二移位寄存器（130）并行使用以对第一测试向量（102）进行时分复用， 以及第二测试矢量（104），用于提供给第一和第二多个测试装置的多个较小测试矢量（102ac; 104ac）。 通过改变第一移位寄存器（110）和第二移位寄存器（130）的大小，可以进行要接触的电子设备的引脚数与所需的测试时间之间的折衷。 第一移位寄存器（110）可以耦合到第一缓冲寄存器（120），并且第二移位寄存器（130）可以耦合到第二缓冲寄存器（140），以增强测试数据的稳定性。 第一移位寄存器（110）和第二移位寄存器（130）可以是较大移位寄存器的分区。 该方法也可以通过将测试结果向量时间解复用到可测试电子设备的输出侧的单个向量中以相反的方式使用。
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公开(公告)号：US07945828B2
公开(公告)日：2011-05-17
申请号：US12093639
申请日：2006-10-23
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31932
摘要： An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (100). The arrangement (10) further comprises space compaction logic (140) comprising a space compaction network (160) having a plurality of compaction domains (162), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network (150) coupled between the plurality of digital outputs (122, 210) and the space compaction network (160), the spreading network being arranged to duplicate each test result from the digital outputs (122,210) to a number of compaction domains (162). This space compaction logic (140), which may be located on the IC 100 or external thereto such as on a test apparatus or on a test interface, reduces the risk of fault cancellation or fault aliasing compared to SCLs without spreading network.
摘要翻译： 集成电路（IC）装置（10）包括具有多个数字输出（122）的数字电路部分（120）的集成电路（100），每个输出被布置成在测试模式下提供测试结果 的集成电路（100）。 布置（10）还包括空间压缩逻辑（140），其包括具有多个压实域（162）的空间压缩网络（160），每个域被布置成将多个测试结果压缩成另外的测试结果，并且 扩展网络（150），其耦合在所述多个数字输出（122,210）和所述空间压缩网络（160）之间，所述扩展网络被布置为将来自所述数字输出（122,210）的每个测试结果复制到多个压缩域 162）。 该空间压缩逻辑（140）可以位于IC 100上或其外部，例如在测试装置或测试接口上，与没有扩展网络的SCL相比，降低了故障消除或故障混叠的风险。
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公开(公告)号：US20100223515A1
公开(公告)日：2010-09-02
申请号：US12063156
申请日：2006-08-09
申请人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
发明人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31719
摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.
摘要翻译： 集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。 提供耦合到扫描链（14）的扫描链修改电路（43,47,70a-c）。 当授权测试时，扫描链修改电路以通过扫描链提供正常移位路径的模式工作。 当测试不被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位期间动态地改变集成电路的外部端子之间的移位路径的长度 。 在一个实施例中，通过运行的密钥比较来控制动态变化。 在其他实施例中，运行密钥比较用于禁止通过扫描链的转移和/或功能电路的操作。
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公开(公告)号：US20090024893A1
公开(公告)日：2009-01-22
申请号：US12093639
申请日：2006-10-23
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/31703 , G01R31/31932
摘要： An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (100). The arrangement (10) further comprises space compaction logic (140) comprising a space compaction network (160) having a plurality of compaction domains (162), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network (150) coupled between the plurality of digital outputs (122, 210) and the space compaction network (160), the spreading network being arranged to duplicate each test result from the digital outputs (122,210) to a number of compaction domains (162). This space compaction logic (140), which may be located on the IC 100 or external thereto such as on a test apparatus or on a test interface, reduces the risk of fault cancellation or fault aliasing compared to SCLs without spreading network.
摘要翻译： 集成电路（IC）装置（10）包括具有多个数字输出（122）的数字电路部分（120）的集成电路（100），每个输出被布置成在测试模式下提供测试结果 的集成电路（100）。 布置（10）还包括空间压缩逻辑（140），其包括具有多个压实域（162）的空间压缩网络（160），每个域被布置成将多个测试结果压缩成另外的测试结果，并且 扩展网络（150），其耦合在所述多个数字输出（122,210）和所述空间压缩网络（160）之间，所述扩展网络被布置为将来自所述数字输出（122,210）的每个测试结果复制到多个压缩域 162）。 该空间压缩逻辑（140）可以位于IC 100上或其外部，例如在测试装置或测试接口上，与没有扩展网络的SCL相比，降低了故障消除或故障混叠的风险。
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