利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.019 秒)

    CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST
    1.
    发明申请
    CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST 有权
    用于测试速度结构测试的时钟控制电路

    公开(公告)号：US20060190781A1

    公开(公告)日：2006-08-24

    申请号：US10906407

    申请日：2005-02-18

    申请人： Henry Farmer ,  Gary Grise ,  David Milton ,  Mark Taylor

    发明人： Henry Farmer ,  Gary Grise ,  David Milton ,  Mark Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31727 ,  G01R31/318533

    摘要： When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.

    摘要翻译： 当使用功能时钟测试ASIC时，时钟根控制电路在根中包含额外的测试逻辑和用于时钟控制的调制台，从而产生非常灵活的控制，可以以多个时钟速率通过时钟信号，并且可以通过 只有一个时钟沿，从而允许所需数量的时钟脉冲通过测试。 该系统使用ASIC中设计的功能时钟和时钟分配树。

    CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST
    2.
    发明申请
    CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST 审中-公开
    用于测试速度结构测试的时钟控制电路

    公开(公告)号：US20060248417A1

    公开(公告)日：2006-11-02

    申请号：US10908123

    申请日：2005-04-28

    申请人： Henry Farmer ,  Gary Grise ,  David Milton ,  Steven Oakland ,  Mark Taylor

    发明人： Henry Farmer ,  Gary Grise ,  David Milton ,  Steven Oakland ,  Mark Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31727 ,  G01R31/318552

    摘要： A clock selection circuit selectively passes one or more clocks into portions of an integrated circuit for testing. In one mode, the selection circuit passes a functional clock into a section of logic for an at speed test under test program control. In another mode, the selection circuit passes a clock other than the functional clock, such at a reduced frequency, in a test mode.

    摘要翻译： 时钟选择电路选择性地将一个或多个时钟传送到用于测试的集成电路的部分。 在一种模式中，选择电路将功能时钟传递到用于在测试程序控制下进行速度测试的逻辑部分。 在另一种模式中，选择电路在测试模式下，以诸如频率降低的功能时钟传递除了功能时钟以外的时钟。

    MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
    5.
    发明申请
    MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) 有权
    用于逻辑内置自检的微控制器（LBIST）

    公开(公告)号：US20070204193A1

    公开(公告)日：2007-08-30

    申请号：US11276413

    申请日：2006-02-28

    申请人： Gary Grise ,  David Lackey ,  Steven Oakland ,  Donald Wheater

    发明人： Gary Grise ,  David Lackey ,  Steven Oakland ,  Donald Wheater

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31724 ,  G01R31/31727

    摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

    摘要翻译： 内置自检（BIST）微控制器集成电路，适用于逻辑验证。 微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合 用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

    TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
    6.
    发明申请
    TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS 有权
    多个异步逻辑域的测试

    公开(公告)号：US20070204194A1

    公开(公告)日：2007-08-30

    申请号：US11276433

    申请日：2006-02-28

    申请人： Gary Grise ,  Vikram Iyengar ,  David Lackey

    发明人： Gary Grise ,  Vikram Iyengar ,  David Lackey

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/318594

    摘要： A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator circuits. The first test pulse generator circuit is electrically coupled to the first pin and the first logic domain. The second test pulse generator circuit is electrically coupled to the second pin and the second logic domain. When a first test signal and N (positive integer) common test enable signals being asserted, the first test pulse generator circuit generates two first test pulses resulting in the first logic domain being tested. When a second test signal and the N common test enable signals being asserted, the second test pulse generator circuit generates two second test pulses resulting in the second logic domain being tested. The first and second pins are connected to a tester.

    摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一和第二引脚，（b）第一和第二逻辑域，以及（c）第一和第二测试脉冲发生器电路。 第一测试脉冲发生器电路电耦合到第一引脚和第一逻辑域。 第二测试脉冲发生器电路电耦合到第二引脚和第二逻辑域。 当第一测试信号和N（正整数）公共测试使能信号被断言时，第一测试脉冲发生器电路产生两个第一测试脉冲，导致第一逻辑域被测试。 当第二测试信号和N个公共测试使能信号被断言时，第二测试脉冲发生器电路产生两个第二测试脉冲，导致第二逻辑域被测试。 第一和第二引脚连接到测试仪。

    FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
    7.
    发明申请
    FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS 失效
    集成电路的功能频率测试

    公开(公告)号：US20060041802A1

    公开(公告)日：2006-02-23

    申请号：US10711075

    申请日：2004-08-20

    申请人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

    发明人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318555 ,  G01R31/318541 ,  H03K3/35625

    摘要： A method and circuits for testing an integrated circuit at functional lock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

    摘要翻译： 一种用于在功能锁定频率下测试集成电路的方法和电路，该方法和电路通过提供一个测试控制器来产生控制信号，该控制信号确保测试仪频率上的扫描链中的测试图形的正确锁定，并且通过在功能时钟频率下测试的逻辑电路传播测

    Non-destructive target marking for image stitching
    8.
    发明授权
    Non-destructive target marking for image stitching 失效
    用于图像拼接的非破坏性目标标记

    公开(公告)号：US5663806A

    公开(公告)日：1997-09-02

    申请号：US538542

    申请日：1995-10-03

    申请人： Gary Grise ,  Jerzy M. Zalesinski

    发明人： Gary Grise ,  Jerzy M. Zalesinski

    IPC分类号： H04N1/04 ,  G06T1/00 ,  H04N1/047 ,  H04N1/12 ,  H04N1/191 ,  H04N1/10 ,  H04N1/053

    CPC分类号： H04N1/128 ,  H04N1/047 ,  H04N1/12 ,  H04N1/1911 ,  H04N2201/04729

    摘要： A scanner using a small, inexpensive CCD array for accurately and easily re-creating an error free reproduction of any scanned image wherein a plurality of laser alignment marks are temporarily projected, from an inexpensive solid state laser via a low cost plastic fiber optic cable, onto the surface of the document, and capturing the image as a number of small segments, along both the horizontal and vertical dimensions of the document onto the surface of the image being scanned. These temporary, projected, alignment marks permit the accurate positioning of adjacent, scanned segments during reconstruction of the scanned document. This scanner can scan documents of any width with an accuracy such that the scanned document can be readily, easily and accurately reassembled regardless of the insensitivity of, or misalignment of the scanning array in the apparatus or the skew of the document relative to the camera doing the scanning.

    摘要翻译： 一种使用小型便宜的CCD阵列的扫描器，用于通过低成本塑料光缆从廉价的固体激光器准确且容易地重新创建其中暂时投射多个激光对准标记的任何扫描图像的无错误再现， 并将文档的水平和垂直尺寸沿着正在扫描的图像的表面上沿数个小段捕获。 这些临时的，投影的对准标记允许在扫描的文件重建期间相邻的被扫描的段的精确定位。 该扫描仪可以以精确度扫描任何宽度的文档，使得扫描的文档可以容易，容易和准确地重新组装，而不管扫描阵列在设备中的不敏感性或不对准，或者文档相对于相机的倾斜。 扫描。