公开(公告)号：US20070283201A1

公开(公告)日：2007-12-06

申请号：US11772340

申请日：2007-07-02

申请人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

发明人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G01R31/318541 ,  H03K3/35625

摘要： A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

摘要翻译： 一种用于通过提供测试控制器产生控制信号的测试控制器的方法和电路，所述控制信号确保在测试器频率下扫描链中的测试图案的正确锁存，并且通过在功能时钟频率下测试的逻辑电路来传播测试图案。

公开(公告)号：US20060041802A1

公开(公告)日：2006-02-23

申请号：US10711075

申请日：2004-08-20

申请人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

发明人： Gary Grise ,  Steven Oakland ,  Anthony Polson ,  Philip Stevens

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G01R31/318541 ,  H03K3/35625

摘要： A method and circuits for testing an integrated circuit at functional lock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

摘要翻译： 一种用于在功能锁定频率下测试集成电路的方法和电路，该方法和电路通过提供一个测试控制器来产生控制信号，该控制信号确保测试仪频率上的扫描链中的测试图形的正确锁定，并且通过在功能时钟频率下测试的逻辑电路传播测

公开(公告)号：US20060248417A1

公开(公告)日：2006-11-02

申请号：US10908123

申请日：2005-04-28

申请人： Henry Farmer ,  Gary Grise ,  David Milton ,  Steven Oakland ,  Mark Taylor

发明人： Henry Farmer ,  Gary Grise ,  David Milton ,  Steven Oakland ,  Mark Taylor

IPC分类号： G01R31/28

CPC分类号： G01R31/31727 ,  G01R31/318552

摘要： A clock selection circuit selectively passes one or more clocks into portions of an integrated circuit for testing. In one mode, the selection circuit passes a functional clock into a section of logic for an at speed test under test program control. In another mode, the selection circuit passes a clock other than the functional clock, such at a reduced frequency, in a test mode.

摘要翻译： 时钟选择电路选择性地将一个或多个时钟传送到用于测试的集成电路的部分。 在一种模式中，选择电路将功能时钟传递到用于在测试程序控制下进行速度测试的逻辑部分。 在另一种模式中，选择电路在测试模式下，以诸如频率降低的功能时钟传递除了功能时钟以外的时钟。

公开(公告)号：US20070204193A1

公开(公告)日：2007-08-30

申请号：US11276413

申请日：2006-02-28

申请人： Gary Grise ,  David Lackey ,  Steven Oakland ,  Donald Wheater

发明人： Gary Grise ,  David Lackey ,  Steven Oakland ,  Donald Wheater

IPC分类号： G01R31/28

CPC分类号： G01R31/31724 ,  G01R31/31727

摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

摘要翻译： 内置自检（BIST）微控制器集成电路，适用于逻辑验证。 微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合 用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

公开(公告)号：US20080062783A1

公开(公告)日：2008-03-13

申请号：US11851613

申请日：2007-09-07

申请人： Arthur BRIGHT ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Quellette ,  Scott Strissel

发明人： Arthur BRIGHT ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Quellette ,  Scott Strissel

IPC分类号： G11C29/00 ,  G11C17/18

CPC分类号： G11C29/4401 ,  G11C29/802

摘要： A design structure for repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

摘要翻译： 一种用于修复包括多个存储器阵列的类型的集成电路的设计结构和用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该设计结构为集成电路提供了一个控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 设计结构还通过控制数据选择器将来自其源的备用控制数据传递到存储器阵列，以控制存储器阵列的冗余逻辑。

公开(公告)号：US20050050415A1

公开(公告)日：2005-03-03

申请号：US10604908

申请日：2003-08-26

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318544

摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

公开(公告)号：US20070258296A1

公开(公告)日：2007-11-08

申请号：US11418052

申请日：2006-05-04

申请人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

发明人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/4401 ,  G11C29/802

摘要： Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

摘要翻译： 公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

公开(公告)号：US20050013187A1

公开(公告)日：2005-01-20

申请号：US10604414

申请日：2003-07-18

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

摘要翻译： 一种用于减少使用冗余eFuse电路制造的半导体器件的测试时间的方法和电熔丝电路设计。 除了保险丝锁存器和图案锁存器以及eFuse电路的其他逻辑元件之外，在每个eFuse电路上还提供两对一多路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 由模式锁存器产生的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”转到下一个锁存器，或者旁路下一个锁存器或锁存在换档链中，这取决于下一个保险丝是否被熔断。 因此，本发明不仅可以串联地转换器件内的每个熔丝锁存器，而且仅使与熔断器相关联的熔丝锁存器能够保持传输“1”到下一个eFuse电路的传输。

公开(公告)号：US20070200597A1

公开(公告)日：2007-08-30

申请号：US11276408

申请日：2006-02-28

申请人： Steven Oakland

发明人： Steven Oakland

IPC分类号： H03K19/173

CPC分类号： H03K5/15013 ,  G06F1/10

摘要： Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

摘要翻译： 公开了一种用于产生相对于时钟输入信号具有固定等待时间的时钟输出信号的时钟发生电路。 当使用多个这样的时钟发生电路将时钟信号馈送到集成电路结构内的不同数字逻辑电路时，延迟时间差（称为偏斜）被最小化。 时钟发生电路的一个实施例包括波形发生器和时序改进的电机。 波形发生器由时钟输入信号计时。 该台式电脑包括触发器，电平敏感锁存器和多路复用器。 触发器和锁存器并联连接，并且每个接收来自波形发生器的波形信号以及时钟输入信号，以便产生输出信号。 多路复用器使用触发器门锁定输出信号并输入时钟输入信号，以产生时钟输出信号。 还公开了用于边缘敏感多路复用器扫描设计的可​​测试的台式电脑。

公开(公告)号：US20060190784A1

公开(公告)日：2006-08-24

申请号：US10906481

申请日：2005-02-22

申请人： Pamela Gillis ,  David Litten ,  Steven Oakland

发明人： Pamela Gillis ,  David Litten ,  Steven Oakland

IPC分类号： G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/2853

摘要： A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each the boundary scan segment.

摘要翻译： 边界扫描寄存器电路和表征测试方法。 边界扫描寄存器电路包括：多个边界扫描单元串联连接，每个边界扫描单元具有锁存器; 用于将边界扫描单元隔离成一个或多个边界扫描段的装置，每个边界扫描段包含不同的边界扫描单元组; 以及用于表征通过每个边界扫描段的信号传播的装置。