Variable slew control for output buffers
    1.
    发明授权
    Variable slew control for output buffers 失效
    输出缓冲器的可变转换控制

    公开(公告)号:US5568081A

    公开(公告)日:1996-10-22

    申请号:US483068

    申请日:1995-06-07

    CPC分类号: H03K19/00361 H03K17/166

    摘要: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

    摘要翻译: 公开了一种用于输出电路的可变转换控制。 摆幅控制电路自动调节摆动节点上的电压被驱动到参考电压的速率,从而使输出设备驱动器的噪声最小化。 在di / dt为高电平时,可变转换控制可以降低转换节点的转换速率,但是当输出驱动器的di / dt较低时,可以使转子节点上的电压以更快的速率下降。

    Fully programmable I/O pin with memory
    2.
    发明授权
    Fully programmable I/O pin with memory 有权
    带可编程I / O引脚的内存

    公开(公告)号:US06577157B1

    公开(公告)日:2003-06-10

    申请号:US09187545

    申请日:1998-11-05

    IPC分类号: H03K19173

    CPC分类号: H03K19/1732

    摘要: The present invention provides a programmable pin that may be selectively configured to operate as a signal pin or a power pin. A programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins may also be used to provide better performance of the entire integrated circuit device and reduce noise in the pins of the integrated circuit device that are signal pins. The programmable pin may also include the function of retaining the last asserted state on the pin. Memory provides further functionality and flexibility in the design of integrated circuit devices.

    摘要翻译: 本发明提供一种可选择性地配置为作为信号引脚或电源引脚工作的可编程引脚。 可编程引脚在集成电路器件的设计中提供了更高的灵活性。 也可以使用可编程引脚来提供整个集成电路器件的更好性能,并降低作为信号引脚的集成电路器件引脚中的噪声。 可编程引脚还可以包括保持引脚上的最后一个置位状态的功能。 内存在集成电路设备的设计中提供了进一步的功能和灵活性。

    Low power high voltage switch with gate bias circuit to minimize power
consumption
    3.
    发明授权
    Low power high voltage switch with gate bias circuit to minimize power consumption 失效
    低功率高压开关,具有栅极偏置电路,以最大限度地降低功耗

    公开(公告)号:US5604711A

    公开(公告)日:1997-02-18

    申请号:US446539

    申请日:1995-05-19

    CPC分类号: G11C16/12 G11C8/08

    摘要: A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.

    摘要翻译: 具有低功率编程电压开关的存储器电路,用于在读取操作期间减少泄漏电流。 该装置包括高压开关,其在编程模式中接收高(例如编程)电压,并且在另一模式(读数)中接收正常范围电压;以及线驱动器,其将选择或非选择电压驱动为字线 或列选择行到存储器阵列中。 在读取模式期间,取消选择的线路驱动器和高压开关以减小的漏电流模式工作,使得在强制通过取消选择的线路驱动器之前,泄漏电流被迫通过选定的线路驱动器及其高电压开关,使得漏电流为 限于所选线路驱动器的数量。