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公开(公告)号：US20190121753A1
公开(公告)日：2019-04-25
申请号：US15793899
申请日：2017-10-25
发明人： Kirill Malkin , Alan Poston , Matthew Jacob
CPC分类号： G06F13/1642 , G06F13/28 , G06F13/4022 , G06F13/4282 , G06F2213/0026
摘要： According to examples, an apparatus may include a memory to which a first queue and a second queue are assigned, in which a storage device is to access data task requests stored in the first queue and the second queue, in which the apparatus is to transfer the first queue to a second apparatus. The apparatus may also include a central processing unit (CPU), the CPU to input data task requests for the storage device into the second queue, in which the second apparatus is to store the first queue in a second memory of the second apparatus, and the storage device is to access data task requests from the first queue stored in the second memory of the second apparatus and data task requests from the second queue stored in the memory to cause the apparatus and the second apparatus to share access to the storage device.
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公开(公告)号：US11068420B2
公开(公告)日：2021-07-20
申请号：US14710492
申请日：2015-05-12
发明人： Kirill Malkin
摘要： A scalable software stack is disclosed. In particular, the present disclosure provides a system and a method directed at allocating logical ownership of memory locations in a shared storage device among two or more associated compute devices that have access to the storage device. The logical ownership allocation can minimize potential conflicts between two simultaneous accesses occurring within the same memory location of the storage device.
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公开(公告)号：US20190124180A1
公开(公告)日：2019-04-25
申请号：US15789394
申请日：2017-10-20
发明人： Frank Dropps , Russell Nicol , Kirill Malkin
IPC分类号： H04L29/06
摘要： A transmitting device can compress a packet prior to transmitting the packet to a receiving device, which then decompresses the packet. The packet can be combined into a single combined packet with other packets within a transmission queue of the same type and that refer to consecutive memory block addresses. A header of the packet can be replaced with a reduced-size header including a sequence number and a flag indicating the header has been replaced with the reduced-size header, if the packet has a consecutive memory block address to that of the most recently transmitted packet. A payload of the packet may also be compressed.
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公开(公告)号：US20180018196A1
公开(公告)日：2018-01-18
申请号：US15650357
申请日：2017-07-14
发明人： Steven J. Dean , Michael Woodacre , Randal S. Passint , Eric C. Fromm , Thomas E. McGee , Michael E. Malewicki , Kirill Malkin
CPC分类号： G06F9/45558 , G06F9/50 , G06F9/5077 , G06F9/54 , G06F2009/45595 , G06Q10/06 , H04L29/08315 , H04L67/1042
摘要： A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.
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公开(公告)号：US11029847B2
公开(公告)日：2021-06-08
申请号：US15353413
申请日：2016-11-16
发明人： Kirill Malkin , Steve Dean , Michael Woodacre , Eng Lim Goh
摘要： In high performance computing, the potential compute power in a data center will scale to and beyond a billion-billion calculations per second (“Exascale” computing levels). Limitations caused by hierarchical memory architectures where data is temporarily stored in slower or less available memories will increasingly limit high performance computing systems from approaching their maximum potential processing capabilities. Furthermore, time spent and power consumed copying data into and out of a slower tier memory will increase costs associated with high performance computing at an accelerating rate. New technologies, such as the novel Zero Copy Architecture disclosed herein, where each compute node writes locally for performance, yet can quickly access data globally with low latency will be required. The result is the ability to perform burst buffer operations and in situ analytics, visualization and computational steering without the need for a data copy or movement.
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公开(公告)号：US10521260B2
公开(公告)日：2019-12-31
申请号：US15650357
申请日：2017-07-14
发明人： Steven J. Dean , Michael Woodacre , Randal S. Passint , Eric C. Fromm , Thomas E. McGee , Michael E. Malewicki , Kirill Malkin
摘要： A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.
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公开(公告)号：US10515027B2
公开(公告)日：2019-12-24
申请号：US15793899
申请日：2017-10-25
发明人： Kirill Malkin , Alan Poston , Matthew Jacob
摘要： According to examples, an apparatus may include a memory to which a first queue and a second queue are assigned, in which a storage device is to access data task requests stored in the first queue and the second queue, in which the apparatus is to transfer the first queue to a second apparatus. The apparatus may also include a central processing unit (CPU), the CPU to input data task requests for the storage device into the second queue, in which the second apparatus is to store the first queue in a second memory of the second apparatus, and the storage device is to access data task requests from the first queue stored in the second memory of the second apparatus and data task requests from the second queue stored in the memory to cause the apparatus and the second apparatus to share access to the storage device.
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公开(公告)号：US10296222B2
公开(公告)日：2019-05-21
申请号：US15339411
申请日：2016-10-31
发明人： Kirill Malkin
摘要： The present system enables more efficient I/O processing by providing a mechanism for maintaining data within the locality of reference. One or more accelerator modules may be implemented within a solid state storage device (SSD). The accelerator modules form a caching storage tier that can receive, store and reproduce data. The one or more accelerator modules may place data into the SSD or hard disk drives based on parameters associated with the data.
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