公开(公告)号：US20240364344A1

公开(公告)日：2024-10-31

申请号：US18140359

申请日：2023-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rachid Kadri ,  Michael Chan

IPC: H03K19/173 ,  H03K19/20 ,  H03M1/78

CPC classification number: H03K19/173 ,  H03K19/20 ,  H03M1/785

Abstract: One aspect provides a programmable logic device. The device includes an input circuit for detecting a multi-level input signal and an output circuit. The input circuit includes: an input pin for receiving the multi-level input signal; first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals; a pair of comparators, each comparator having a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators. The output circuit includes a third programmable voltage generator to generate a third multi-level voltage signal, an output pin, and a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.

公开(公告)号：US20190028112A1

公开(公告)日：2019-01-24

申请号：US16066800

申请日：2016-01-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rachid Kadri

IPC: H03M1/12 ,  G06F1/04 ,  G06F13/16 ,  G06F12/0831

Abstract: In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.

公开(公告)号：US10771081B2

公开(公告)日：2020-09-08

申请号：US16066800

申请日：2016-01-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rachid Kadri

IPC: H03M1/12 ,  G06F1/04 ,  G06F12/0831 ,  G06F13/16 ,  H03M1/46

Abstract: In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.