公开(公告)号：US20240098898A1

公开(公告)日：2024-03-21

申请号：US17949732

申请日：2022-09-21

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin Kent Benedict ,  Chi Kim Sides ,  Paul Danna ,  Michael Chan

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K3/4038 ,  H05K2201/09545 ,  H05K2203/0207

Abstract: One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.

公开(公告)号：US10681832B1

公开(公告)日：2020-06-09

申请号：US16433857

申请日：2019-06-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kevin B. Leigh ,  Everett Salinas ,  Richard Barnett ,  Michael Chan

IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14 ,  H01L23/498 ,  G02B6/42 ,  H05K1/11

Abstract: A high-density universally-configurable system board architecture for use with multiple mid-board optic (MBO) type configurations is provided. The system board comprises a switch application specific integrated circuit (ASIC) assembly, a plurality of MBO interfaces comprising a plurality of via-in-pad plated over (VIPPO) vias, and a plurality of mounting holes. Each MBO interface is configured to mate with a soldered-down MBO assembly or a socket instance comprising a socketized MBO assembly. Each socketized MBO assembly comprises an interposer comprising a plurality of VIPPO vias, where the bottom contact pad of each VIPPO via is thicker than the top contact pad. Either configuration is facilitated without the need to modify the system board layout.

公开(公告)号：US20240364344A1

公开(公告)日：2024-10-31

申请号：US18140359

申请日：2023-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rachid Kadri ,  Michael Chan

IPC: H03K19/173 ,  H03K19/20 ,  H03M1/78

CPC classification number: H03K19/173 ,  H03K19/20 ,  H03M1/785

Abstract: One aspect provides a programmable logic device. The device includes an input circuit for detecting a multi-level input signal and an output circuit. The input circuit includes: an input pin for receiving the multi-level input signal; first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals; a pair of comparators, each comparator having a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators. The output circuit includes a third programmable voltage generator to generate a third multi-level voltage signal, an output pin, and a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.

公开(公告)号：US20230292436A1

公开(公告)日：2023-09-14

申请号：US17689611

申请日：2022-03-08

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Paul Danna ,  Chi Kim Sides ,  Wayne Vuong ,  Michael Chan

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K2201/09263 ,  H05K2201/09609

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

公开(公告)号：US11937373B2

公开(公告)日：2024-03-19

申请号：US17689611

申请日：2022-03-08

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Paul Danna ,  Chi Kim Sides ,  Wayne Vuong ,  Michael Chan

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/09263 ,  H05K2201/09609

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.