BOOTING PROCESSORS
    1.
    发明申请

    公开(公告)号:US20220083345A1

    公开(公告)日:2022-03-17

    申请号:US17419387

    申请日:2019-04-30

    Abstract: Examples for booting a processor are described herein. In an example, a pure hardware parameter associated with a processor, from amongst a plurality of processors, is determined to identify the processor. A firmware appropriate for booting of the processor is identified, based on the identified processor. Then, a Serial Peripheral Interface Read-Only Memory (SPI-ROM) is selected for loading the identified firmware to boot the identified processor. As part of selecting the firmware, the identified firmware is loaded to the SPI-ROM.

    Basic input output system updates

    公开(公告)号:US11409607B1

    公开(公告)日:2022-08-09

    申请号:US17374081

    申请日:2021-07-13

    Abstract: Example implementations relate to Basic Input Output System updates. In some examples, a computing device can include a memory, a processor to, in response to completion of a Basic Input/Output System (BIOS) update, generate and store a boot status variable in the memory, determine whether the BIOS update was successful, in response to the BIOS update being successful, delete the boot status variable from the memory and perform a power event, and in response to the BIOS update being unsuccessful, perform a BIOS recovery.

    DISPLAY MODE SETTING DETERMINATIONS

    公开(公告)号:US20220270538A1

    公开(公告)日:2022-08-25

    申请号:US17635573

    申请日:2019-10-18

    Abstract: Examples for generating a common video signal for an integrated GPU and the graphical processing device, based on a common display mode setting, are described. In an example, a common display mode setting is determined based on a first set of display mode settings supported by the integrated GPU and a second set of display mode settings supported by the graphical processing device. Based on the common display mode setting, video signals for the integrated GPU and the graphical processing device are generated.

    TRANISTIONARY FIRMWARE PACKAGES
    7.
    发明申请

    公开(公告)号:US20220147343A1

    公开(公告)日:2022-05-12

    申请号:US17419392

    申请日:2019-03-11

    Abstract: In an example implementation according to aspects of the present disclosure, a system comprising a memory and a controller coupled to the memory. The controller receives a transitionary firmware package. The controller extracts a transitionary firmware from the transitionary firmware package. The controller writes the transitionary firmware to memory, wherein the transitionary firmware comprises a reduced functionality for each of a set of central processing units. The controller identifies the CPU currently installed in the system and determines a full featured firmware corresponding to that CPU. The controller writes the full featured firmware to the memory.

    STORAGE HASH VALUES
    8.
    发明申请

    公开(公告)号:US20220137846A1

    公开(公告)日:2022-05-05

    申请号:US17419066

    申请日:2019-07-19

    Abstract: An example system may include a processor and a non-transitory machine-readable storage medium storing instructions executable by the processer to record, responsive to a first boot of a computing device, storage device identification data and storage device communication path data for a storage device of the computing device, generate a storage device hash value, characterizing a storage configuration of the computing device, from the recorded storage device identification data and the recorded storage device communication path data, and store the storage device hash value to be compared to a subsequently generated storage device hash value characterizing an updated storage configuration of the computing device at a second boot of the computing device.

    STORING POST CODES IN ELECTRONIC TAGS

    公开(公告)号:US20220113979A1

    公开(公告)日:2022-04-14

    申请号:US17419492

    申请日:2019-06-27

    Abstract: The present subject matter relates to techniques for storing POST codes in electronic tags. In an example, a POST code corresponding to each test of a Power ON Self-Test (POST) process may be stored in a Complementary Metal-Oxide Semiconductor (CMOS) chip of a motherboard. The POST code may be indicative of a status of a respective test of the POST process. The POST code corresponding to each test of the POST process is simultaneously stored in a memory of an electronic tag. The electronic tag may be communicatively coupled to the motherboard and the CMOS chip. The POST codes are retrievable from the memory of the electronic tag by an end user of the computing device when the motherboard is powered OFF.

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