PERIPHERAL ELECTRONIC DEVICE REPRESENTATION VIA UNIFORM TRANSMISSION PROTOCOL

    公开(公告)号:US20240095204A1

    公开(公告)日:2024-03-21

    申请号:US18262107

    申请日:2021-01-28

    CPC classification number: G06F13/387 G06F13/102

    Abstract: In one example in accordance with the present disclosure, a computing device is described. The computing device includes a configurable logic element. The configurable logic element 1) connects to a number of peripheral electronic devices, with at least one peripheral electronic device having a different native protocol relative to another peripheral electronic device and 2) prepares and packages a number of signals to be transmitted across a uniform transmission protocol. The computing device also includes a communication pathway to transmit packaged signals to a driver using the uniform transmission protocol. The computing device also includes the driver to 1) unpack the number of signals from the aggregated data transmission and 2) represents the number of peripheral electronic devices to an operating system of the computing device.

    ELECTRONIC DEVICES EMPLOYING OPTICAL COMMUNICATIONS

    公开(公告)号:US20240235676A1

    公开(公告)日:2024-07-11

    申请号:US18557391

    申请日:2021-04-30

    CPC classification number: H04B10/112 H02J50/10 H02J50/90 H04B10/503

    Abstract: An electronic device employing optical communications including a light cell array, each light cell individually operable to output a controllable collimated light beam, the light beams of the light cell array to form a data encoded optical output signal to transmit to a destination electronic device. A photocell array receives a data encoded optical input signal from the destination electronic device, each photocell to provide an output signal representative of an amount of energy received from the optical input signal. A controller measures an overlap of the optical input signal with the photocell array based on the output signals of the array of photocells, and adjusts a position of the photocell array based on the measured overlap to align the photocell array with the with the optical input signal.

    ANCHOR LOCATION CALIBRATION
    5.
    发明公开

    公开(公告)号:US20230375657A1

    公开(公告)日:2023-11-23

    申请号:US18248681

    申请日:2020-10-12

    CPC classification number: G01S5/0242 H04W64/00 G01S13/76

    Abstract: In an example implementation according to aspects of the present disclosure, a wireless anchor node comprises a wireless communication interface and a processor communicatively coupled to the wireless communication interface. The processor receives a wireless signal from a source access node. The location of the source access node is verified. The processor determines a distance measurement between the wireless anchor node and the source access node based on the wireless signal and transfers the distance measurement between the wireless anchor node and the source access node to a target access node over an intermediate anchor node. In response, the processor receives a location error from the target access node over the intermediate anchor node. The location of the target access node is verified. The processor calibrates the distance measurement between the wireless anchor node and the source access node based on the location error.

    Compressible energizing elements
    8.
    发明授权

    公开(公告)号:US12204697B2

    公开(公告)日:2025-01-21

    申请号:US18261103

    申请日:2021-01-25

    Abstract: In some examples, a device can include a magnetic element coupled to a cap, a compressible energizing element surrounding the magnetic element, an electrical device coupled to the compressible energizing element to provide a current, and a processor resource to adjust a current applied to the compressible energizing element based on a selected resistance level.

    RECONFIGURABLE COMPUTING FABRIC FOR MACHINE LEARNING PROCESSING

    公开(公告)号:US20230394364A1

    公开(公告)日:2023-12-07

    申请号:US18250517

    申请日:2020-10-29

    CPC classification number: G06N20/00

    Abstract: One example provides a reconfigurable computing fabric to manage machine learning (ML) processing including a configurable interconnect structure and a number programmable logic blocks each having a configurable set of operations. For each of a number of fabric configurations of the computing fabric, each programmable logic block has a corresponding set of operations and the interconnect structure has a corresponding data path structure to interconnect the programmable logic blocks with one another and with inputs and outputs of the computing fabric. The programmable logic blocks include an input/output block having a set of operations including to provide virtual interfaces to receive external session requests for ML processing from request sources, and an elastic AI/ML processing block having a set of operations including to configure a number of AI/ML engines with a session implementation for each external session request and each of a number of event-driven internal session requests.

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